Seth Copen Goldstein Publications Listed by Topic

@misc{goldstein-cm5users94,
  title = {Active Messages: A Communication Foundation for Parallel
     Programming Models},
  howpublished = {CM-5 Users Group},
  author = {Goldstein, Seth Copen},
  address = {Santa Fe, NM},
  year = {1994},
  month = {February},
  keywords = {Active Messages,Parallel Computing}
}

@inproceedings{culler-sc93,
  author = {Culler, David E. and Dusseau, Andrea and Goldstein, Seth
     Copen and Krishnamurthy, Arvind and Lumetta, Steven and
     von~Eicken, Thorsten and Yelick, Katherine},
  title = {Parallel Programming in Split-C},
  booktitle = {Proceedings of the Supercomputing '93 Conference},
  pages = {262-273},
  year = {1993},
  address = {Portland, OR},
  month = {November},
  keywords = {Active Messages,Parallel Computing},
  url = {http://www.cs.cmu.edu/~seth/papers/culler-sc93.pdf}
}

@inproceedings{SpertusGSvECD93,
  author = {Spertus, Ellen and Goldstein, Seth Copen and Schauser,
     Klaus Erik and von~Eicken, Thorsten and Culler, David E. and
     Dally, William J.},
  title = {{Evaluation of Mechanisms for Fine-Grained Parallel
     Programs in the J-Machine and the CM-5}},
  booktitle = {Proceedings of the 20th International Symposium on
     Computer Architecture (ISCA)},
  address = {San Diego, CA},
  month = {May},
  year = {1993},
  keywords = {Active Messages, Parallel Computing,Threaded Abstract
     Machine (TAM)},
  url = {http://www.cs.cmu.edu/~seth/papers/SpertusGSvECD93.pdf}
}

@article{CullerGSvE93,
  author = {Culler, David E. and Goldstein, Seth Copen and Schauser,
     Klaus Erik and von~Eicken, Thorsten},
  title = {{TAM --- a compiler controlled threaded abstract machine}},
  journal = {Journal of Parallel and Distributed Computing},
  year = {1993},
  volume = {18},
  pages = {347-370},
  month = {July},
  abstract = {The Threaded Abstract Machine (TAM) refines dataflow
     execution models to address the critical constraints that modern
     parallel architectures place on the compilation of
     general-purpose parallel programming languages. TAM defines a
     self-scheduled machine language of parallel threads, which
     provides a path from dataflow-graph program representations to
     conventional control flow. The most important feature of TAM is
     the way it exposes the interaction between the handling of
     asynchronous message events, the scheduling of computation, and
     the utilization of the storage hierarchy. This paper provides a
     complete description of TAM and codifies the model in terms of a
     pseudo machine language TL0. Issues in compilation from a high
     level parallel language to TL0 are discussed in general and
     specifically in regard to the Id90 language. The implementation
     of TL0 on the CM-5 multiprocessor is explained in detail. Using
     this implementation, a cost model is developed for the various
     TAM primitives. The TAM approach is evaluated on sizable Id90
     programs on a 64 processor system. The scheduling hierarchy of
     quanta and threads is shown to provide substantial locality while
     tolerating long latencies. This allows the average thread
     scheduling cost to be extremely low.},
  url = {http://www.cs.cmu.edu/~seth/papers/CullerGSvE93.pdf},
  keywords = {Active Messages, Parallel Computing,Threaded Abstract
     Machine (TAM)}
}

@inproceedings{voneicken-isca92,
  author = {von~Eicken, Thorsten and Culler, David E. and Goldstein,
     Seth Copen and Schauser, Klaus Erik},
  title = {{Active Messages}: A Mechanism for Integrated Communication
     and Computation},
  month = {May},
  booktitle = {Proceedings of the 19th International Symposium on
     Computer Architecture (ISCA)},
  address = {Gold Coast, Australia},
  pages = {430--440},
  year = {1992},
  url = {http://www.cs.cmu.edu/~seth/papers/voneicken-isca92.pdf},
  abstract = {The design challenge for large-scale multiprocessors is
     (1) to minimize communication overhead, (2) allow communication
     to overlap computation, and (3) coordinate the two without
     sacrificing processor cost/performance. We show that existing
     message passing multiprocessors have unnecessarily high
     communication costs. Research prototypes of message driven
     machines demonstrate low communication overhead, but poor
     processor cost/performance. We introduce a simple communication
     mechanism, {\em Active Messages}, show that it is intrinsic to
     both architectures, allows cost effective use of the hardware,
     and offers tremendous flexibility. Implementations on nCUBE/2 and
     CM-5 are described and evaluated using a split-phase
     shared-memory extension to C, {\em Split-C}. We further show that
     active messages are sufficient to implement the dynamically
     scheduled languages for which message driven machines were
     designed. With this mechanism, latency tolerance becomes a
     programming/compiling concern. Hardware support for active
     messages is desirable and we outline a range of enhancements to
     mainstream processors.},
  keywords = {Active Messages, Parallel Computing}
}

@inproceedings{bkirby-iros07,
  author = {Kirby, Brian and Aksak, Burak and Hoburg, James F. and
     Mowry, Todd C. and Pillai, Padmanabhan},
  title = {A Modular Robotic System Using Magnetic Force Effectors},
  booktitle = {In Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems (IROS '07)},
  year = {2007},
  month = {October},
  abstract = {One of the primary impediments to building ensembles
     with many modular robots is the complexity and number of
     mechanical mechanisms used to construct the individual modules.
     As part of the Claytronics project---which aims to build very
     large ensembles of modular robots---we investigate how to
     simplify each module by eliminating moving parts and reducing the
     number of mechanical mechanisms on each robot by using
     force-at-a-distance actuators. Additionally, we are also
     investigating the feasibility of using these unary actuators to
     improve docking performance, implement intermodule adhesion,
     power transfer, communication, and sensing.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/bkirby-iros07.pdf}
}

@inproceedings{karagozler-iros07,
  author = {Karagozler, Mustafa Emre and Campbell, Jason D. and
     Fedder, Gary K. and Goldstein, Seth Copen and Weller, Michael
     Philetus and Yoon, Byung W.},
  title = {Electrostatic Latching for Inter-module Adhesion, Power
     Transfer, and Communication in Modular Robots},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems IROS '07},
  year = {2007},
  month = {October},
  abstract = {A simple and robust inter-module latch is possibly the
     most important component of a modular robotic system. This paper
     describes a latch based on capacitive coupling which not only
     provides significant adhesion forces, but can also be used for
     inter-module power transmission and communication. The key
     insight that enables electrostatic adhesion to be effective at
     the macroscale is to combine flexible electrodes with a geometery
     that uses shear forces to provide adhesion. To measure the
     effectiveness of our latch we incorporated it into a 28cm x 28cm
     x 28cm modular robot. The result is a latch which requires almost
     zero static power and yet can hold over 0.6N/cm^2 of latch
     area.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros07.pdf}
}

@inproceedings{bkirby-iros07,
  author = {Kirby, Brian and Aksak, Burak and Hoburg, James F. and
     Mowry, Todd C. and Pillai, Padmanabhan},
  title = {A Modular Robotic System Using Magnetic Force Effectors},
  booktitle = {In Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems (IROS '07)},
  year = {2007},
  month = {October},
  abstract = {One of the primary impediments to building ensembles
     with many modular robots is the complexity and number of
     mechanical mechanisms used to construct the individual modules.
     As part of the Claytronics project---which aims to build very
     large ensembles of modular robots---we investigate how to
     simplify each module by eliminating moving parts and reducing the
     number of mechanical mechanisms on each robot by using
     force-at-a-distance actuators. Additionally, we are also
     investigating the feasibility of using these unary actuators to
     improve docking performance, implement intermodule adhesion,
     power transfer, communication, and sensing.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/bkirby-iros07.pdf}
}

@inproceedings{karagozler-iros07,
  author = {Karagozler, Mustafa Emre and Campbell, Jason D. and
     Fedder, Gary K. and Goldstein, Seth Copen and Weller, Michael
     Philetus and Yoon, Byung W.},
  title = {Electrostatic Latching for Inter-module Adhesion, Power
     Transfer, and Communication in Modular Robots},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems IROS '07},
  year = {2007},
  month = {October},
  abstract = {A simple and robust inter-module latch is possibly the
     most important component of a modular robotic system. This paper
     describes a latch based on capacitive coupling which not only
     provides significant adhesion forces, but can also be used for
     inter-module power transmission and communication. The key
     insight that enables electrostatic adhesion to be effective at
     the macroscale is to combine flexible electrodes with a geometery
     that uses shear forces to provide adhesion. To measure the
     effectiveness of our latch we incorporated it into a 28cm x 28cm
     x 28cm modular robot. The result is a latch which requires almost
     zero static power and yet can hold over 0.6N/cm^2 of latch
     area.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros07.pdf}
}

@inproceedings{weller-iros07,
  author = {Weller, Michael Philetus and Karagozler, Mustafa Emre and
     Kirby, Brian and Campbell, Jason D. and Goldstein, Seth Copen},
  title = {Movement Primitives for an Orthogonal Prismatic
     Closed-Lattice-Constrained Self-Reconfiguring Module},
  booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
     IEEE International Conference on Intelligent Robots and Systems
     (IROS) '07},
  year = {2007},
  month = {October},
  keywords = {Adhesion, Robotics, Planning, Claytronics},
  abstract = {We describe a new set of prismatic movement primitives
     for cubic modular robots. Our approach appears more practical
     than previous metamodule-based approaches. We also describe
     recent hardware developments in our cubic robot modules that have
     sufficient stiffness and actuator strength so that when they work
     together they can realize, in earth's gravity, all of the motion
     primitives we describe here.}
}

@inproceedings{chelcea-async07,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Area Optimizations for Dual-Rail Circuits Using
     Relative-Timing Analysis},
  booktitle = {Proceedings of the 13th IEEE International Symposium on
     Asynchronous Circuits and Systems},
  year = {2007},
  address = {Berkeley, CA},
  month = {March},
  pages = {117--128},
  abstract = {Future deep sub-micron technologies will be
     characterized by large parametric variations, which could make
     asynchronous design an attractive solution for use on large
     scale. However, the investment in asynchronous CAD tools does not
     approach that in synchronous ones. Even when asynchronous tools
     leverage existing synchronous toolflows, they introduce large
     area and speed overheads. This paper proposes several heuristic
     and optimal algorithms, based on timing interval analysis, for
     improving existing asynchronous CAD solutions by optimizing area.
     The optimized circuits are 2.4 times smaller for an optimal
     algorithm and 1.8 times smaller for a heuristic one than the
     existing solutions. The optimized circuits are also shown to be
     resilient to large parametric variations, yielding better
     average-case latencies than their synchronous counterparts.},
  url = {http://www.cs.cmu.edu/~seth/papers/chelcea-async07.pdf},
  keywords = {Asychronous Circuits, CAD}
}

@inproceedings{dac07-gcp,
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Global Critical Path: A Tool for System-Level Timing
     Analysis},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {June},
  address = {San Diego, CA},
  pages = {783--786},
  abstract = {An effective method for focusing optimization effort on
     the most important parts of a design is to examine those elements
     on the critical path. Traditionally, the critical path is defined
     at the RTL level, as the longest path in the combinational logic
     between clocked reisters. In this paper, we present a
     system-level timing analysis technique to define the concept of a
     Global Critical Path (GCP), for predicting system-level
     performance. We show how the GCP can be used as a theoretical and
     practical tool for understanding, summarizing and optimizing the
     behavior of highly concurrent self-timed circuits. We formally
     define the GCP and show how it can be constructed using a
     discrete event model and hardware profiling techniques. The GCP
     provides valuable insight into the control-path behavior of
     circuits and in finding system-level bottlenecks. We have
     incorporated the GCP construction and analysis framework into a
     high-level synthesis and simulation toolchain, thus enabling
     complete automation in modeling, analysis and optimization.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path, System
     modeling, Hardware profiling}
}

@inproceedings{venkataramani-iccad07,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  title = {Operation Chaining Asynchronous Pipelined Circuits},
  booktitle = {ICCAD},
  month = {November},
  year = {2007},
  keywords = {Asychronous Circuits, CAD, Global Critical Path}
}

@inproceedings{dac07-sr,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Self-Resetting Latches for Asynchronous Micro-Pipelines},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {June},
  address = {San Diego, CA},
  pages = {986--989},
  keywords = {Asychronous Circuits},
  abstract = {Asynchronous circuits are increasingly attractive as low
     power or high-performance replacements to synchronous designs. A
     key part of these circuits are asynchronous micropipelines;
     unfortunatelly, the existing micropipeline styles either improve
     performance or decrease power consumption, but not both. Very
     often, the pipeline register plays a crucial role in these cost
     metrics. In this paper we introduce a new register design, called
     self-resetting latches, for asynchronous micropipelines which
     bridges the gap between fast, but power hungry, latch-based
     designs and slow, but low power, flip-flop designs. The
     energy-delay metric for large asynchronous systems implemented
     with self-resetting latches is, on average, 41\% better than
     latch-based designs and 15\% better than flip-flop designs.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-sr.pdf}
}

@article{venkataramani-tcad06,
  title = {Hardware Compilation of Application-Specific Memory Access
     Interconnect},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  journal = {IEEE Transactions on Computer Aided Design of Integrated
     Circuits and Systems},
  year = {2006},
  volume = {25},
  number = {5},
  pages = {756--771},
  issn = {0278-0070},
  abstract = {{A major obstacle to successful high-level synthesis
     (HLS) of large-scale application-specified integrated circuit
     systems is the presence of memory accesses to a shared-memory
     subsystem. The latency to access memory is often not statically
     predictable, which creates problems for scheduling operations
     dependent on memory reads. More fundamental is that dependences
     between accesses may not be statically provable (e.g., if the
     specification language permits pointers), which introduces
     memory-consistency problems. Addressing these issues with static
     scheduling results in overly conservative circuits, and thus,
     most state-of-the-art HLS tools limit memory systems to those
     that have predictable latencies and limit programmers to
     specifications that forbid arbitrary memory-reference patterns. A
     new HLS framework for the synthesis and optimization of memory
     accesses (SOMA) is presented. SOMA enables specifications to
     include arbitrary memory references (e.g., pointers) and allows
     the memory system to incorporate features that might cause the
     latency of a memory access to vary dynamically. This results in
     raising the level of abstraction in the input specification,
     enabling faster design times. SOMA synthesizes a memory access
     network (MAN) architecture that facilitates dynamic scheduling
     and ordering of memory accesses. The paper describes a basic MAN
     construction technique that illustrates how dynamic ordering
     helps in efficiently maintaining memory consistency and how
     dynamic scheduling helps alleviate the variable-latency problem.
     Then, it is shown how static analysis of the access patterns can
     be used to optimize the MAN. One optimization changes the MAN
     interconnect topology to increase concurrence. A second
     optimization reduces the synchronization overhead necessary to
     maintain memory consistency. Postlayout experiments demonstrate
     that SOMA's application-specific MAN construction significantly
     improves power and performance for a range of benchmarks.}},
  keywords = {Asychronous Circuits, Spatial
     Computing,Phoenix,Network-on-a-chip},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tcad06.pdf}
}

@inproceedings{venkataramani-iccad06,
  title = {Leveraging Protocol Knowledge in Slack Matching},
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design (ICCAD)},
  year = {2006},
  address = {San Jose, CA},
  month = {November},
  abstract = {{Stalls, due to mis-matches in communication rates, are
     a major performance obstacle in pipelined circuits. If the rate
     of data production is faster than the rate of consumption, the
     resulting design performs slower than when the communication rate
     is matched. This can be remedied by inserting pipeline buffers
     (to temporarily hold data), allowing the producer to proceed if
     the consumer is not ready to accept data. The problem of deciding
     which channels need these buffers (and how many) for an arbitrary
     communication profile is called the slack matching problem; the
     optimal solution to this problem has been shown to be
     NP-complete. \par In this paper, we present a heuristic that uses
     knowledge of the communication protocol to explicitly model these
     bottlenecks, and an iterative algorithm to progressively remove
     these bottlenecks by inserting buffers. We apply this algorithm
     to asynchronous circuits, and show that it naturally handles
     large designs with arbitrarily cyclic and acyclic topologies,
     which exhibit various types of control choice. The heuristic is
     efficient, achieving linear time complexity in practice, and
     produces solutions that (a) achieve up to 60\% performance
     speedup on large media processing kernels, and (b) can either be
     verified to be optimal, or the approximation margin can be
     bounded. }},
  keywords = {Asychronous Circuits, Spatial Computing, CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad06.pdf}
}

@techreport{venkataramani-tr06,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Budiu,
     Mihai and Goldstein, Seth Copen},
  title = {Modeling the Global Critical Path in Concurrent Systems},
  institution = {Carnegie Mellon University},
  year = {2006},
  number = {CMU-CS-06-144},
  month = {August},
  abstract = {We show how the global critical path can be used as a
     practical tool for understanding, optimizing and summarizing the
     behavior of highly concurrent self-timed circuits. Traditionally,
     critical path analysis has been applied to DAGs, and thus was
     constrained to combinatorial sub-circuits. We formally define the
     global critical path (GCP) and show how it can be constructed
     using only local information that is automatically derived
     directly from the circuit. We introduce a form of Production
     Rules, which can accurately determine the GCP for a given input
     vector, even for modules which exhibit choice and early
     termination. \par The GCP provides valuable insight into the
     control behavior of the application, which help in formulating
     new optimizations and re-formulating existing ones to use the GCP
     knowledge. We have constructed a fully automated framework for
     GCP detection and analysis, and have incorporated this framework
     into a high-level synthesis tool-chain. We demonstrate the
     effectiveness of the GCP framework by re-formulating two
     traditional CAD optimizations to use the GCP, yielding efficient
     algorithms which improve circuit power (by up to 9\%) and
     performance (by up to 60\%) in our experiments.},
  keywords = {Asychronous Circuits, Spatial Computing,CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tr06.pdf}
}

@inproceedings{mahim-asplos06,
  title = {Tartan: Evaluating Spatial Computation for Whole Program
     Execution},
  author = {Mishra, Mahim and Callahan, Timothy J and Chelcea, Tiberiu
     and Venkataramani, Girish and Budiu, Mihai and Goldstein, Seth
     Copen},
  booktitle = {12th ACM International Conference on Architecture
     Support for Programming Languages and Operating Systems
     (ASPLOS)},
  year = {2006},
  pages = {163--174},
  address = {San Jose, CA},
  month = {October},
  abstract = {Spatial Computing (SC) has been shown to be an
     energy-efficient model for implementing program kernels. In this
     paper we explore the feasibility of using SC for more than small
     kernels. To this end, we evaluate the performance and energy
     efficiency of entire applications on Tartan, a general-purpose
     architecture which integrates a reconfigurable fabric (RF) with a
     superscalar core. Our compiler automatically partitions and
     compiles an application into an instruction stream for the core
     and a configuration for the RF. We use a detailed simulator to
     capture both timing and energy numbers for all parts of the
     system. \par Our results indicate that a hierarchical RF
     architecture, designed around a scalable interconnect, is
     instrumental in harnessing the benefits of spatial computation.
     The interconnect uses static configuration and routing at the
     lower levels and a packet-switched, dynamically-routed network at
     the top level. Tartan is most energy-efficient when almost all of
     the application is mapped to the RF, indicating the need for the
     RF to support most general-purpose programming constructs. Our
     initial investigation reveals that such a system can provide, on
     average, an order of magnitude improvement in energy-delay
     compared to an aggressive superscalar core on single-threaded
     workloads.},
  keywords = {Asychronous Circuits, Spatial Computing, Reconfigurable
     Computing,Phoenix, Tartan},
  url = {http://www.cs.cmu.edu/~seth/papers/mahim-asplos06.pdf}
}

@techreport{koes-tr05,
  author = {Koes, David Ryan and Chelcea, Tiberiu and Onyeama, Charles
     and Goldstein, Seth Copen},
  title = {Adding Faster with Application Specific Early Termination},
  institution = {Carnegie Mellon University},
  year = {2005},
  number = {CMU-CS-05-101},
  pages = {20},
  month = {May},
  url = {http://www.cs.cmu.edu/~seth/papers/koes-tr05.pdf},
  abstract = {This paper presents a methodology for improving the
     speed of high-speed adders. As a starting point, a previously
     proposed method, called speculative completion, is used in which
     fast- terminating additions are automatically detected. Unlike
     the previous design, the method proposed in this paper is able to
     adapt dynamically to (1) application-specific behavior and (2) to
     adder- specific behavior, resulting in a higher detection rate of
     fast additions and, consequently, a faster average-case speed for
     addition. Our experimental results show detection rates of over
     99\%, and adder average-case speed improvements of up to 14.\%.},
  keywords = {Asychronous Circuits}
}

@inproceedings{venkataramani-isss05,
  title = {SOMA: A Tool for Synthesizing and Optimizing Memory
     Accesses in ASICs},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis (CODES-ISSS)},
  year = {2005},
  isbn = {1-59593-161-9},
  pages = {231-236},
  address = {Jersey City, NJ, USA},
  month = {September},
  abstract = {Arbitrary memory dependencies and variable latency
     memory systems are major obstacles to the synthesis of
     large-scale ASIC systems in high-level synthesis. This paper
     presents SOMA, a synthesis framework for constructing Memory
     Access Network (MAN) architectures that inherently enforce memory
     consistency in the presence of dynamic memory access
     dependencies. A fundamental bottleneck in any such network is
     arbitrating between concurrent accesses to a shared memory
     resource. To alleviate this bottleneck, SOMA uses an
     application-specific concurrency analysis technique to predict
     the dynamic memory parallelism profile of the application. This
     is then used to customize the MAN architecture. Depending on the
     parallelism profile, the MAN may be optimized for latency,
     throughput or both. The optimized MAN is automatically
     synthesized into gate-level structural Verilog using a flexible
     library of network building blocks. SOMA has been successfully
     integrated into an automated C-to-hardware synthesis flow, which
     generates standard cell circuits from unrestricted ANSI-C
     programs. Post-layout experiments demonstrate that application
     specific MAN construction significantly improves power and
     performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix,
     CAD,Compilers:Memory Optimizations},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-isss05.pdf}
}

@inproceedings{venkataramani-iwls05,
  title = {{HLS} Support for Unconstrained Memory Accesses},
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
     Seth Copen},
  booktitle = {IEEE 14th International Workshop on Logic Synthesis
     (IWLS)},
  year = {2005},
  address = {Lake Arrowhead, CA},
  month = {June},
  abstract = {A major obstacle in high-level synthesis (HLS) of
     large-scale ASIC systems is memory access patterns. Typically,
     most state-of-the-art HLS tools impose constraints on the memory
     references in the source application, requiring them to exhibit
     predictable access patterns, and/or requiring dependencies
     between them to be statically determinable. This paper addresses
     the HLS problem when such constraints are relaxed. We present an
     analysis infrastructure that can be used within any HLS toolflow
     for synthesizing circuits from high-level abstractions, such as
     ANSI-C, where no assumptions can be made about memory access
     latencies, and where dependencies between memory references can
     only be disambiguated dynamically at runtime (pointer aliasing).
     We start by describing a generic framework to build a
     dependence-aware, fully distributed, although often conservative,
     memory-access network (MAN) for a given memory-dependence graph.
     Then, we propose a suite of optimizations to customize the MAN
     for the given specification. All these techniques guarantee
     memory coherency. Experimental results on Mediabench benchmarks,
     show that such an approach succeeds in maintaining high levels of
     parallelism, while ensuring memory coherency. The optimizations
     succeed in lowering the synchronization overhead by as much as
     4x.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls05.pdf}
}

@inproceedings{budiu-asplos04,
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Spatial Computation},
  booktitle = {International Conference on Architectural Support for
     Programming Languages and Operating Systems (ASPLOS)},
  pages = {14--26},
  month = {October},
  address = {Boston, MA},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-asplos04.pdf},
  abstract = {This paper describes a computer architecture that relies
     on the direct translation of high-level language programs into
     {\em Spatial Computation} (SC) hardware structures. SC program
     implementations are completely distributed, without any
     centralized control. SC circuits are optimized for {\em wires} at
     the expense of computation units. \par In this paper we
     investigate a particular implementation SC structures called ASH
     (Application-Specific Hardware). Under the assumption that
     computation is cheaper than communication, ASH replicates
     computation units to simplify interconnect, building a system
     which uses very simple, completely dedicated communication
     channels. As a consequence, communication on the datapath never
     requires arbitration; the only arbitration required is for
     accessing memory. ASH relies on very simple hardware primitives,
     using no associative structures, no multiported register files,
     no scheduling logic, no broadcast, and no clocks. As a
     consequence, ASH hardware is fast and extremely power efficient.
     \par In this work we demonstrate three features of ASH: (1) that
     such architectures can be built by automatic compilation of C
     programs, (2) that distributed computation is in some respects
     fundamentally different from monolithic superscalar processors
     and (3) that ASIC implementations of ASH use 3 orders of
     magnitude less energy compared to high-end superscalar
     processors, while being within a factor of two in performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix}
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {April},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing}
}

@inproceedings{venkataramani-iwls04,
  title = {{C} to Asynchronous Dataflow Circuits: An End-to-End
     Toolflow},
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE 13th International Workshop on Logic Synthesis
     (IWLS)},
  address = {Temecula, CA},
  month = {June},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls04.pdf},
  abstract = {We present a complete toolflow that translates ANSI-C
     programs into asynchronous circuits. The toolflow is built around
     a compiler that converts C into a functional dataflow
     intermediate representation, exposing instruction-level, pipeline
     and memory parallelism. The compiler performs optimizations and
     converts the intermediate representation into pipelined
     asynchronous circuits, with no centralized controllers. In the
     resulting circuits, control is distributed, communication is
     achieved through local wires, and arbitration for datapath
     resources is unnecessary. Circuits automatically synthesized from
     Mediabench kernels exhibit substantially better energy-delay than
     either single-issue processors or aggressive superscalar cores.},
  keywords = {Asychronous Circuits,Spatial Computing,Phoenix,CAD}
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics,},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {January},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics}
}

@inproceedings{goldstein-waci06,
  author = {Goldstein, Seth Copen},
  title = {Brain in a Bottle},
  booktitle = {Wild and Crazy Ideas Session of ASPLOS},
  year = {2006},
  month = {October},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-waci06.pdf},
  keywords = {Brain, Parallel Computing, Self-Assembly}
}

@inproceedings{chelcea-async07,
  author = {Chelcea, Tiberiu and Venkataramani, Girish and Goldstein,
     Seth Copen},
  title = {Area Optimizations for Dual-Rail Circuits Using
     Relative-Timing Analysis},
  booktitle = {Proceedings of the 13th IEEE International Symposium on
     Asynchronous Circuits and Systems},
  year = {2007},
  address = {Berkeley, CA},
  month = {March},
  pages = {117--128},
  abstract = {Future deep sub-micron technologies will be
     characterized by large parametric variations, which could make
     asynchronous design an attractive solution for use on large
     scale. However, the investment in asynchronous CAD tools does not
     approach that in synchronous ones. Even when asynchronous tools
     leverage existing synchronous toolflows, they introduce large
     area and speed overheads. This paper proposes several heuristic
     and optimal algorithms, based on timing interval analysis, for
     improving existing asynchronous CAD solutions by optimizing area.
     The optimized circuits are 2.4 times smaller for an optimal
     algorithm and 1.8 times smaller for a heuristic one than the
     existing solutions. The optimized circuits are also shown to be
     resilient to large parametric variations, yielding better
     average-case latencies than their synchronous counterparts.},
  url = {http://www.cs.cmu.edu/~seth/papers/chelcea-async07.pdf},
  keywords = {Asychronous Circuits, CAD}
}

@inproceedings{dac07-gcp,
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Global Critical Path: A Tool for System-Level Timing
     Analysis},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {June},
  address = {San Diego, CA},
  pages = {783--786},
  abstract = {An effective method for focusing optimization effort on
     the most important parts of a design is to examine those elements
     on the critical path. Traditionally, the critical path is defined
     at the RTL level, as the longest path in the combinational logic
     between clocked reisters. In this paper, we present a
     system-level timing analysis technique to define the concept of a
     Global Critical Path (GCP), for predicting system-level
     performance. We show how the GCP can be used as a theoretical and
     practical tool for understanding, summarizing and optimizing the
     behavior of highly concurrent self-timed circuits. We formally
     define the GCP and show how it can be constructed using a
     discrete event model and hardware profiling techniques. The GCP
     provides valuable insight into the control-path behavior of
     circuits and in finding system-level bottlenecks. We have
     incorporated the GCP construction and analysis framework into a
     high-level synthesis and simulation toolchain, thus enabling
     complete automation in modeling, analysis and optimization.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path, System
     modeling, Hardware profiling}
}

@inproceedings{venkataramani-iccad07,
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  title = {Operation Chaining Asynchronous Pipelined Circuits},
  booktitle = {ICCAD},
  month = {November},
  year = {2007},
  keywords = {Asychronous Circuits, CAD, Global Critical Path}
}

@inproceedings{venkataramani-iccad06,
  title = {Leveraging Protocol Knowledge in Slack Matching},
  author = {Venkataramani, Girish and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM International Conference on Computer-Aided
     Design (ICCAD)},
  year = {2006},
  address = {San Jose, CA},
  month = {November},
  abstract = {{Stalls, due to mis-matches in communication rates, are
     a major performance obstacle in pipelined circuits. If the rate
     of data production is faster than the rate of consumption, the
     resulting design performs slower than when the communication rate
     is matched. This can be remedied by inserting pipeline buffers
     (to temporarily hold data), allowing the producer to proceed if
     the consumer is not ready to accept data. The problem of deciding
     which channels need these buffers (and how many) for an arbitrary
     communication profile is called the slack matching problem; the
     optimal solution to this problem has been shown to be
     NP-complete. \par In this paper, we present a heuristic that uses
     knowledge of the communication protocol to explicitly model these
     bottlenecks, and an iterative algorithm to progressively remove
     these bottlenecks by inserting buffers. We apply this algorithm
     to asynchronous circuits, and show that it naturally handles
     large designs with arbitrarily cyclic and acyclic topologies,
     which exhibit various types of control choice. The heuristic is
     efficient, achieving linear time complexity in practice, and
     produces solutions that (a) achieve up to 60\% performance
     speedup on large media processing kernels, and (b) can either be
     verified to be optimal, or the approximation margin can be
     bounded. }},
  keywords = {Asychronous Circuits, Spatial Computing, CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iccad06.pdf}
}

@techreport{venkataramani-tr06,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Budiu,
     Mihai and Goldstein, Seth Copen},
  title = {Modeling the Global Critical Path in Concurrent Systems},
  institution = {Carnegie Mellon University},
  year = {2006},
  number = {CMU-CS-06-144},
  month = {August},
  abstract = {We show how the global critical path can be used as a
     practical tool for understanding, optimizing and summarizing the
     behavior of highly concurrent self-timed circuits. Traditionally,
     critical path analysis has been applied to DAGs, and thus was
     constrained to combinatorial sub-circuits. We formally define the
     global critical path (GCP) and show how it can be constructed
     using only local information that is automatically derived
     directly from the circuit. We introduce a form of Production
     Rules, which can accurately determine the GCP for a given input
     vector, even for modules which exhibit choice and early
     termination. \par The GCP provides valuable insight into the
     control behavior of the application, which help in formulating
     new optimizations and re-formulating existing ones to use the GCP
     knowledge. We have constructed a fully automated framework for
     GCP detection and analysis, and have incorporated this framework
     into a high-level synthesis tool-chain. We demonstrate the
     effectiveness of the GCP framework by re-formulating two
     traditional CAD optimizations to use the GCP, yielding efficient
     algorithms which improve circuit power (by up to 9\%) and
     performance (by up to 60\%) in our experiments.},
  keywords = {Asychronous Circuits, Spatial Computing,CAD, Global
     Critical Path},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-tr06.pdf}
}

@inproceedings{venkataramani-isss05,
  title = {SOMA: A Tool for Synthesizing and Optimizing Memory
     Accesses in ASICs},
  author = {Venkataramani, Girish and Bjerregaard, Tobias and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE/ACM/IFIP International Conference on
     Hardware/Software Codesign and System Synthesis (CODES-ISSS)},
  year = {2005},
  isbn = {1-59593-161-9},
  pages = {231-236},
  address = {Jersey City, NJ, USA},
  month = {September},
  abstract = {Arbitrary memory dependencies and variable latency
     memory systems are major obstacles to the synthesis of
     large-scale ASIC systems in high-level synthesis. This paper
     presents SOMA, a synthesis framework for constructing Memory
     Access Network (MAN) architectures that inherently enforce memory
     consistency in the presence of dynamic memory access
     dependencies. A fundamental bottleneck in any such network is
     arbitrating between concurrent accesses to a shared memory
     resource. To alleviate this bottleneck, SOMA uses an
     application-specific concurrency analysis technique to predict
     the dynamic memory parallelism profile of the application. This
     is then used to customize the MAN architecture. Depending on the
     parallelism profile, the MAN may be optimized for latency,
     throughput or both. The optimized MAN is automatically
     synthesized into gate-level structural Verilog using a flexible
     library of network building blocks. SOMA has been successfully
     integrated into an automated C-to-hardware synthesis flow, which
     generates standard cell circuits from unrestricted ANSI-C
     programs. Post-layout experiments demonstrate that application
     specific MAN construction significantly improves power and
     performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix,
     CAD,Compilers:Memory Optimizations},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-isss05.pdf}
}

@inproceedings{budiu-async04,
  title = {Translating ANSI C to Asynchronous Circuits},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-async04.pdf},
  booktitle = {10th IEEE International Symposium on Asynchronous
     Circuits and Systems (ASYNC '04)},
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  address = {Crete, Greece},
  year = {2004},
  month = {April},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Phoenix,Reconfigurable Computing,Spatial
     Computing}
}

@inproceedings{venkataramani-iwls04,
  title = {{C} to Asynchronous Dataflow Circuits: An End-to-End
     Toolflow},
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  booktitle = {IEEE 13th International Workshop on Logic Synthesis
     (IWLS)},
  address = {Temecula, CA},
  month = {June},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-iwls04.pdf},
  abstract = {We present a complete toolflow that translates ANSI-C
     programs into asynchronous circuits. The toolflow is built around
     a compiler that converts C into a functional dataflow
     intermediate representation, exposing instruction-level, pipeline
     and memory parallelism. The compiler performs optimizations and
     converts the intermediate representation into pipelined
     asynchronous circuits, with no centralized controllers. In the
     resulting circuits, control is distributed, communication is
     achieved through local wires, and arbitration for datapath
     resources is unnecessary. Circuits automatically synthesized from
     Mediabench kernels exhibit substantially better energy-delay than
     either single-issue processors or aggressive superscalar cores.},
  keywords = {Asychronous Circuits,Spatial Computing,Phoenix,CAD}
}

@incollection{goldstein-mn03,
  title = {Molecules, Gates, Circuits, Computer},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-mn03.pdf},
  booktitle = {Molecular Nanoelectronics,},
  author = {Goldstein, Seth Copen and Budiu, Mihai},
  year = {2003},
  editor = {Mark A. Reed and Takhee Lee},
  publisher = {American Scientific Publishers},
  address = {Stevenson Ranch, CA},
  month = {January},
  isbn = {1-588883-006-3},
  keywords = {Asychronous Circuits,CAD,Electronic Nanotechnology,Fault
     and Defect Tolerance,Reconfigurable Computing,Spatial
     Computing,electronic nanotechnology,molecular electronics}
}

@inproceedings{goldstein-foresight01,
  author = {Goldstein, Seth Copen and Ellenbogen, James and Almassiam,
     David and Brown, Matt and Cannarsa, Mark and Klein, Jesse and
     Schell, Schuyler and Washburn, Geoff and Ziegler, Matthew M},
  title = {MolSpice: Designing Molecular Logic Circuits},
  booktitle = {Ninth Foresight Conference on Molecular
     Nanotechnology},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-foresight01.pdf},
  year = {2001},
  month = {November},
  address = {Santa Clara, CA},
  keywords = {Electronic Nanotechnology, Molecular Electronics, CAD}
}

@inproceedings{cadambi-fpl01,
  title = {Static Profile-driven Compilation for FPGAs},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fpl01.pdf},
  booktitle = {Proceedings of the 11th International Conference on
     Field-Programmable Logic and Applications},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Belfast, Northern Ireland},
  year = {2001},
  month = {August},
  keywords = {CAD,Reconfigurable Computing}
}

@techreport{budiu-tr00,
  title = {BitValue Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-tr00.pdf},
  booktitle = {CMU CS Technical Report, CMU-CS-00-141},
  author = {Budiu, Mihai and Goldstein, Seth Copen},
  institution = {Carnegie Mellon University},
  year = {2000},
  month = {June},
  see = {budiu-europar00},
  keywords = {CAD,Compilers:CASH,Reconfigurable Computing}
}

@inproceedings{cadambi-iccd00,
  title = {Efficient Place and Route for Pipeline Reconfigurable
     Architectures},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-iccd00.pdf},
  booktitle = {ICCD '00},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  address = {Austin, TX},
  year = {2000},
  month = {September},
  keywords = {CAD,Place and Route}
}

@inproceedings{budiu-europar00,
  title = {{BitValue} Inference: Detecting and Exploiting Narrow
     Bitwidth Computations},
  author = {Budiu, Mihai and Sakr, Majd and Walker, Kevin and
     Goldstein, Seth Copen},
  booktitle = {Proceedings of the 2000 Europar Conference},
  year = {2000},
  volume = {1900},
  pages = {969--979},
  month = {August},
  issn = {0302-9743},
  series = {Lecture Notes in Computer Science},
  publisher = {Springer Verlag},
  address = {Munich, Germany},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-europar00.pdf},
  also = {CMU CS Technical Report, CMU-CS-00-141, October 2000.},
  abstract = {We present a compiler algorithm called BitValue, which
     can discover both unused and constant bits in dusty-deck C
     programs. BitValue uses forward and backward dataflow analyses,
     generalizing constant-folding and dead-code detection at the
     bit-level. This algorithm enables compiler optimizations which
     target special processor architectures for computing on
     non-standard bitwidths. Using this algorithm we show that up to
     31\% of the computed bytes are thrown away (for programs from
     SpecINT95 and Mediabench). A compiler for reconfigurable hardware
     uses this algorithm to achieve substantial reductions (up to
     20-fold) in the size of the synthesized circuits.},
  keywords = {Spatial Computing,Reconfigurable
     Computing,Phoenix,PipeRench,CAD}
}

@inproceedings{cadambi-fccm99,
  title = {CPR: A Configuration Profiling Tool},
  url = {http://www.cs.cmu.edu/~seth/papers/cadambi-fccm99.pdf},
  booktitle = {7th Annual IEEE Symposium on Field-Programmable Custom
     Computing Machines (FCCM '99)},
  author = {Cadambi, Srihari and Goldstein, Seth Copen},
  year = {1999},
  pages = {104},
  address = {Napa Valley, CA},
  month = {April},
  keywords = {CAD,Reconfigurable Computing,Place And Route}
}

@inproceedings{bkirby-iros07,
  author = {Kirby, Brian and Aksak, Burak and Hoburg, James F. and
     Mowry, Todd C. and Pillai, Padmanabhan},
  title = {A Modular Robotic System Using Magnetic Force Effectors},
  booktitle = {In Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems (IROS '07)},
  year = {2007},
  month = {October},
  abstract = {One of the primary impediments to building ensembles
     with many modular robots is the complexity and number of
     mechanical mechanisms used to construct the individual modules.
     As part of the Claytronics project---which aims to build very
     large ensembles of modular robots---we investigate how to
     simplify each module by eliminating moving parts and reducing the
     number of mechanical mechanisms on each robot by using
     force-at-a-distance actuators. Additionally, we are also
     investigating the feasibility of using these unary actuators to
     improve docking performance, implement intermodule adhesion,
     power transfer, communication, and sensing.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/bkirby-iros07.pdf}
}

@inproceedings{ashley-rollman-derosa-iros07wksp,
  author = {Ashley-Rollman, Michael P. and De Rosa, Michael and
     Srinivasa, Siddhartha S. and Pillai, Padmanabhan and Goldstein,
     Seth Copen and Campbell, Jason D.},
  title = {Declarative Programming for Modular Robots},
  booktitle = {Workshop on Self-Reconfigurable Robots/Systems and
     Applications at {IROS '07}},
  year = {2007},
  month = {October},
  keywords = {Programming Models, Planning, Claytronics},
  abstract = {Because of the timing, complexity, and asynchronicity
     challenges common in modular robot software we have recently
     begun to explore new programming models for modular robot
     ensembles. In this paper we apply two of those models to a
     metamodule-based shape planning algorithm and comment on the
     differences between the two approaches. Our results suggest that
     declarative programming can provide several advantages over more
     traditional imperative approaches, and that the differences
     between declarative programming styles can themselves contribute
     leverage to different parts of the problem domain.}
}

@inproceedings{karagozler-iros07,
  author = {Karagozler, Mustafa Emre and Campbell, Jason D. and
     Fedder, Gary K. and Goldstein, Seth Copen and Weller, Michael
     Philetus and Yoon, Byung W.},
  title = {Electrostatic Latching for Inter-module Adhesion, Power
     Transfer, and Communication in Modular Robots},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems IROS '07},
  year = {2007},
  month = {October},
  abstract = {A simple and robust inter-module latch is possibly the
     most important component of a modular robotic system. This paper
     describes a latch based on capacitive coupling which not only
     provides significant adhesion forces, but can also be used for
     inter-module power transmission and communication. The key
     insight that enables electrostatic adhesion to be effective at
     the macroscale is to combine flexible electrodes with a geometery
     that uses shear forces to provide adhesion. To measure the
     effectiveness of our latch we incorporated it into a 28cm x 28cm
     x 28cm modular robot. The result is a latch which requires almost
     zero static power and yet can hold over 0.6N/cm^2 of latch
     area.},
  keywords = {Actuation, Adhesion, Claytronics, Robotics},
  url = {http://www.cs.cmu.edu/~claytronics/papers/karagozler-iros07.pdf}
}

@inproceedings{funiak-iros07,
  author = {Funiak, Stanislav and Pillai, Padmanabhan and Campbell,
     Jason D. and Goldstein, Seth Copen},
  title = {Internal Localization of Modular Robot Ensembles},
  booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
     IEEE International Conference on Intelligent Robots and Systems
     (IROS) '07},
  year = {2007},
  month = {October},
  abstract = {The determination of the relative position and pose of
     every robot in a modular robotic ensemble is a necessary
     preliminary step for most modular robotic tasks. Localization is
     particularly important when the modules make local noisy
     observations and are not significantly constrained by inter-robot
     latches. In this paper, we propose a robust hierarchical approach
     to the {\em internal localization} problem that uses normalized
     cut to guide an incremental solution to incorporating the
     observations. A key component of our algorithm is a method to
     reduce the cost of normalized cut computations. The result is a
     scalable algorithm that works for large, non-homogeneous
     ensembles. We evaluate our algorithm in simulation on ensembles
     of up to 10,000 modules.},
  keywords = {Probabilistic Inference, Sensing, Localization,
     Distributed Algorithms, Claytronics}
}

@inproceedings{ashley-rollman-iros07,
  author = {Ashley-Rollman, Michael P. and Goldstein, Seth Copen and
     Lee, Peter and Mowry, Todd C. and Pillai, Padmanabhan},
  title = {Meld: A Declarative Approach to Programming Ensembles},
  booktitle = {Proceedings of the IEEE International Conference on
     Intelligent Robots and Systems {IROS '07}},
  year = {2007},
  month = {October},
  keywords = {Programming Languages, Claytronics},
  abstract = {This paper presents Meld, a programming language for
     modular robots, i.e., for independently executing robots where
     inter-robot communication is limited to immediate neighbors. Meld
     is a declarative language, based on P2, a logic-programming
     language originally designed for programming overlay networks. By
     using logic programming, the code for an ensemble of robots can
     be written from a global perspective, as opposed to a large
     collection of independent robot views. This greatly simplifies
     the thought process needed for programming large ensembles.
     Initial experience shows that this also leads to a considerable
     reduction in code size and complexity. An initial implementation
     of Meld has been completed and has been used to demonstrate its
     effectiveness in the Claytronics simulator. Early results
     indicate that Meld programs are considerably more concise (more
     than 20x shorter) than programs written in C++, while running
     nearly as efficiently.}
}

@inproceedings{weller-iros07,
  author = {Weller, Michael Philetus and Karagozler, Mustafa Emre and
     Kirby, Brian and Campbell, Jason D. and Goldstein, Seth Copen},
  title = {Movement Primitives for an Orthogonal Prismatic
     Closed-Lattice-Constrained Self-Reconfiguring Module},
  booktitle = {Workshop on Self-Reconfiguring Modular Robotics at the
     IEEE International Conference on Intelligent Robots and Systems
     (IROS) '07},
  year = {2007},
  month = {October},
  keywords = {Adhesion, Robotics, Planning, Claytronics},
  abstract = {We describe a new set of prismatic movement primitives
     for cubic modular robots. Our approach appears more practical
     than previous metamodule-based approaches. We also describe
     recent hardware developments in our cubic robot modules that have
     sufficient stiffness and actuator strength so that when they work
     together they can realize, in earth's gravity, all of the motion
     primitives we describe here.}
}

@inproceedings{derosa-rss06,
  author = {De Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  booktitle = {Robotics: Science and Systems Workshop on
     Self-Reconfigurable Modular Robots},
  title = {Distributed Watchpoints: Debugging Very Large Ensembles of
     Robots},
  month = {August},
  year = {2006},
  keywords = {Claytronics, Modular Robotics, Debugging, Distributed
     Systems},
  address = {Philadelphia, PA},
  url = {http://www.cs.cmu.edu/~seth/papers/derosa-rss06.pdf},
  abstract = {We describe a debugging tool for modular robotics that
     introduces the concept of distributed watchpoint triggers. This
     technique can initiate debugging actions (system halt, global
     snapshot, logging, etc.) in an ensemble of robots based on
     temporal, physical, and logical conditions distributed over
     multiple robots. Our technique is specifically designed to be
     effective in debugging modular robotic ensembles, where many
     important types of failure conditions can be detected within
     small, physically connected subsets of the total ensemble.}
}

@inproceedings{bhat06,
  author = {Bhat, Preethi Srinivas and Kuffner, James and Goldstein,
     Seth Copen and Srinivasa, Siddhartha},
  title = {Hierarchical Motion Planning for Self-reconfigurable
     Modular Robots},
  booktitle = {2006 IEEE/RSJ International Confernce on Intelligent
     Robots and Systems (IROS)},
  year = {2006},
  month = {October},
  keywords = {Claytronics, Planning, Modular Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/bhat06.pdf}
}

@inproceedings{derosa-icra06,
  author = {De Rosa, Michael and Goldstein, Seth Copen and Lee, Peter
     and Campbell, Jason D. and Pillai, Padmanabhan},
  title = {Scalable Shape Sculpting via Hole Motion: Motion Planning
     in Lattice-Constrained Module Robots},
  month = {May},
  booktitle = {Proceedings of the 2006 {IEEE} International Conference
     on Robotics and Automation (ICRA '06)},
  year = {2006},
  keywords = {Claytronics, Programmable Matter, Planning, Modular
     Robotics},
  url = {http://www.cs.cmu.edu/~seth/papers/derosa-icra06.pdf},
  abstract = {We describe a novel shape formation algorithm for
     ensembles of 2-dimensional lattice-arrayed modular robots, based
     on the manipulation of regularly shaped voids within the lattice
     (``holes''). The algorithm is massively parallel and fully
     distributed. Constructing a goal shape requires time propor-
     tional only to the complexity of the desired target geometry.
     Construction of the shape by the modules requires no global
     communication nor broadcast floods after distribution of the
     target shape. Results in simulation show 97.3\% shape compliance
     in ensembles of approximately 60,000 modules, and we believe that
     the algorithm will generalize to 3D and scale to handle millions
     of modules.}
}

@inproceedings{karagozler-rascal06,
  title = {Ultralight Modular Robotic Building blocks for the Rapid
     Deployment of Planetary Outposts},
  booktitle = {Revolutionary Aerospace Systems Concepts Academic
     Linkage (RASC-AL) Forum 2006},
  author = {Karagozler, Mustafa Emre and Kirby, Brian and Lee, W.J.
     and Marinelli, Eugene and Ng, T.C. and Weller, Michael and
     Goldstein, Seth Copen},
  year = {2006},
  month = {May},
  address = {Cape Canaveral, FL},
  url = {http://www.cs.cmu.edu/~seth/papers/karagozler-rascal06.pdf},
  keywords = {Claytronics,Modular Robotics,Robotics}
}

@misc{goldstein-popsci05,
  title = {2029 The 3-D Fax Machine Brings Back the House Call},
  howpublished = {Headline from the Future, Popular Science Magazine},
  author = {Goldstein, Seth Copen},
  year = {2005},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-popsci05.pdf},
  month = {March},
  pages = {34},
  keywords = {Claytronics}
}

@inproceedings{kirby-aaai05,
  author = {Kirby, Brian and Campbell, Jason D. and Aksak, Burak and
     Pillai, Padmanabhan and Hoburg, James F. and Mowry, Todd C. and
     Goldstein, Seth Copen},
  title = {Catoms: Moving Robots Without Moving Parts},
  url = {http://www.cs.cmu.edu/~seth/papers/kirby-aaai05.pdf},
  booktitle = {AAAI (Robot Exhibition)},
  pages = {1730--1},
  year = {2005},
  month = {July},
  address = {Pittsburgh, PA},
  keywords = {Claytronics, Robotics}
}

@inproceedings{aksak-sensys05,
  author = {Aksak, Burak and Bhat, Preethi Srinivas and Campbell,
     Jason D. and De Rosa, Michael and Funiak, Stanislav and Gibbons,
     Phillip B. and Goldstein, Seth Copen and Guestrin, Carlos and
     Gupta, Ashish and Helfrich, Casey and Hoburg, James F. and Kirby,
     Brian and Kuffner, James and Lee, Peter and Mowry, Todd C. and
     Pillai, Padmanabhan and Ravichandran, Ram and Rister, Benjamin D.
     and Seshan, Srinivasan and Sitti, Metin and Yu, Haifeng},
  title = {Demo Abstract: Claytronics---highly scalable
     communications, sensing, and actuation networks.},
  booktitle = {Proceedings of the 3rd international conference on
     Embedded networked sensor systems (SenSys)},
  year = {2005},
  pages = {299},
  url = {http://www.cs.cmu.edu/~seth/papers/aksak-sensys05.pdf},
  doi = {http://doi.acm.org/10.1145/1098918.1098964},
  keywords = {Claytronics, Programmable Matter}
}

@article{goldstein-computer05,
  author = {Goldstein, Seth Copen and Campbell, Jason D. and Mowry,
     Todd C.},
  title = {Programmable Matter},
  journal = {IEEE Computer},
  volume = {38},
  number = {6},
  pages = {99--101},
  year = {2005},
  month = {June},
  keywords = {Claytronics, Programmable Matter},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein-computer05.pdf}
}

@inproceedings{goldstein05,
  author = {Goldstein, Seth Copen and Mowry, Todd C. and Campbell,
     Jason D. and Lee, Peter and Pillai, Padmanabhan and Hoburg, James
     F. and Gibbons, Phillip B. and Guestrin, Carlos and Kuffner,
     James and Kirby, Brian and Rister, Benjamin D. and De Rosa,
     Michael and Funiak, Stanislav and Aksak, Burak and Sukthankar,
     Rahul},
  title = {The Ensemble Principle},
  booktitle = {13th Foresight Conference of Advanced Nanotechnogy},
  url = {http://www.cs.cmu.edu/~seth/papers/goldstein05.pdf},
  year = {2005},
  month = {October},
  address = {San Francisco, CA},
  keywords = {Claytronics, Robotics}
}