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Nonphotolithographic nanoscale memory density prospects
DeHon, A.
Goldstein, S.C.
Kuekes, P.J.
Lincoln, P.
Comput. Sci. Dept., California Inst. of Technol., Pasadena, CA, USA;
This paper appears in: Nanotechnology, IEEE Transactions on
Publication Date: March 2005
Volume: 4,
Issue: 2
On page(s): 215- 228
ISSN: 1536-125X
INSPEC Accession Number: 8328842
Digital Object Identifier: 10.1109/TNANO.2004.837849
Posted online: 2005-03-14 08:31:03.0
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Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations.
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Controlled Indexing
molecular electronics
nanoelectronics
nanolithography
nanowires
self-assembly
storage management
switches
Non-controlled Indexing
high defect rate
memory densities
memory organization
molecular scale electronic wires
nanoscale circuits
nonphotolithographic nanoscale memory density prospects
photolithography
power requirement
self-assembly
switches
wire pitches
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Defect tolerance
electronic nanotechnology
memory density
memory organization
molecular electronics
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Deterministic addressing of nanoscale devices assembled at sublithographic pitches, DeHon, A.
Nanotechnology, IEEE Transactions on
On page(s): 681- 687, Volume: 4, Issue: 6, Nov. 2005
Abstract |
Full Text: PDF (384)
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