Nonphotolithographic Nanoscale Memory Density Prospects

 

IEEE Transactions on Nanotechnology

Andre DeHon, Seth Copen Goldstein, Phil Kuekes, and Patrick Lincoln

volume 4, pages 215–228

March, 2005

Abstract


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@article{lincoln-tnano05,
  title = {Nonphotolithographic Nanoscale Memory Density Prospects},
  abstract = {Technologies are now emerging to construct
     molecular-scale electronic wires and switches using bottom-up
     self-assembly. This opens the possibility of constructing
     nanoscale circuits and memories where active devices are just a
     few nanometers square and wire pitches may be on the order of ten
     nanometers. The features can be defined at this scale without
     using photolithography. The available assembly techniques have
     relatively high defect rates compared to conventional
     lithographic integrated circuits and can only produce very
     regular structures. Nonetheless, with proper memory organization,
     it is reasonable to expect these technologies to provide memory
     densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active
     power requirements under 0.6 W/Tb/s for random read operations.},
  url = {http://www.cs.cmu.edu/~seth/papers/lincoln-tnano05.pdf},
  journal = {IEEE Transactions on Nanotechnology},
  author = {DeHon, Andre and Goldstein, Seth Copen and Kuekes, Phil
     and Lincoln, Patrick},
  year = {2005},
  month = {March},
  volume = {4},
  issue = {2},
  pages = {215-228},
  keywords = {Fault and Defect Tolerance, electronic nanotechnology,
     memory density, memory organization, molecular electronics},
  doi = {10.1109/TNANO.2004.837849}
}

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