# Why area might reduce power in nanoscale CMOS

In IEEE International Symposium on Circuits and Systems, 2005, (ISCAS 2005)

Paul Beckett and Seth Copen Goldstein

volume 3, pages 2329–2332, Kobe, Japan

May, 2005

## Abstract

@inproceedings{beckett-iscas05,
title = {Why area might reduce power in nanoscale CMOS},
url = {http://www.cs.cmu.edu/~seth/papers/beckett-iscas05.pdf},
booktitle = {IEEE International Symposium on Circuits and Systems,
2005, (ISCAS 2005)},
author = {Beckett, Paul and Goldstein, Seth Copen},
year = {2005},
pages = {2329-2332},
volume = {3},
month = {May},
abstract = {In this paper we explore the relationship between power
and area. By exploiting parallelism (and thus using more area)
one can reduce the switching frequency allowing a reduction in
VDD which results in a reduction in power. Under a scaling regime
which allows threshold voltage to increase as VDD decreases we
find that dynamic and subthreshold power loss in CMOS exhibit a
dependence on area proportional to A^((\sigma^-3)/\sigma) while
gate leakage power proportional to A^((\sigma^-6)/\sigma) and
short circuit power A^((\sigma^-6)/\sigma). Thus, with the large
number of devices at our disposal we can exploit techniques such
as spatial computing--tailoring the program directly to the
hardware--to overcome the negative effects of scaling. The value
of s describes the effectiveness of the technique for a
particular circuit and/or algorithm--for circuits that exhibit a
value of \sigma <= 3, power will be a constant or reducing
function of area. We briefly speculate on how \sigma might be
influenced by a move to nanoscale technology.},
keywords = {Electronic Nanotechnology,Power,Energy}
}