Global Critical Path: A Tool for System-Level Timing Analysis

 

In Proceedings of the 44th ACM/IEEE Design Automation Conference

Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein

pages 783–786, San Diego, CA

June, 2007

Abstract


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@inproceedings{dac07-gcp,
  author = {Venkataramani, Girish and Budiu, Mihai and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Global Critical Path: A Tool for System-Level Timing
     Analysis},
  booktitle = {Proceedings of the 44th ACM/IEEE Design Automation
     Conference},
  year = {2007},
  month = {June},
  address = {San Diego, CA},
  pages = {783--786},
  abstract = {An effective method for focusing optimization effort on
     the most important parts of a design is to examine those elements
     on the critical path. Traditionally, the critical path is defined
     at the RTL level, as the longest path in the combinational logic
     between clocked reisters. In this paper, we present a
     system-level timing analysis technique to define the concept of a
     Global Critical Path (GCP), for predicting system-level
     performance. We show how the GCP can be used as a theoretical and
     practical tool for understanding, summarizing and optimizing the
     behavior of highly concurrent self-timed circuits. We formally
     define the GCP and show how it can be constructed using a
     discrete event model and hardware profiling techniques. The GCP
     provides valuable insight into the control-path behavior of
     circuits and in finding system-level bottlenecks. We have
     incorporated the GCP construction and analysis framework into a
     high-level synthesis and simulation toolchain, thus enabling
     complete automation in modeling, analysis and optimization.},
  url = {http://www.cs.cmu.edu/~seth/papers/dac07-gcp.pdf},
  keywords = {Asychronous Circuits, CAD, Global Critical Path, System
     modeling, Hardware profiling}
}

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