Spatial Computation

 

In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein

pages 14–26, Boston, MA

October, 2004

Abstract


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@inproceedings{budiu-asplos04,
  author = {Budiu, Mihai and Venkataramani, Girish and Chelcea,
     Tiberiu and Goldstein, Seth Copen},
  title = {Spatial Computation},
  booktitle = {International Conference on Architectural Support for
     Programming Languages and Operating Systems (ASPLOS)},
  pages = {14--26},
  month = {October},
  address = {Boston, MA},
  year = {2004},
  url = {http://www.cs.cmu.edu/~seth/papers/budiu-asplos04.pdf},
  abstract = {This paper describes a computer architecture that relies
     on the direct translation of high-level language programs into
     {\em Spatial Computation} (SC) hardware structures. SC program
     implementations are completely distributed, without any
     centralized control. SC circuits are optimized for {\em wires} at
     the expense of computation units. \par In this paper we
     investigate a particular implementation SC structures called ASH
     (Application-Specific Hardware). Under the assumption that
     computation is cheaper than communication, ASH replicates
     computation units to simplify interconnect, building a system
     which uses very simple, completely dedicated communication
     channels. As a consequence, communication on the datapath never
     requires arbitration; the only arbitration required is for
     accessing memory. ASH relies on very simple hardware primitives,
     using no associative structures, no multiported register files,
     no scheduling logic, no broadcast, and no clocks. As a
     consequence, ASH hardware is fast and extremely power efficient.
     \par In this work we demonstrate three features of ASH: (1) that
     such architectures can be built by automatic compilation of C
     programs, (2) that distributed computation is in some respects
     fundamentally different from monolithic superscalar processors
     and (3) that ASIC implementations of ASH use 3 orders of
     magnitude less energy compared to high-end superscalar
     processors, while being within a factor of two in performance.},
  keywords = {Asychronous Circuits, Spatial Computing,Phoenix}
}

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Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04), April, 2004.
C to Asynchronous Dataflow Circuits: An End-to-End Toolflow
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Translating ANSI C to Asynchronous Circuits
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04), April, 2004.
C to Asynchronous Dataflow Circuits: An End-to-End Toolflow
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein. In IEEE 13th International Workshop on Logic Synthesis (IWLS), June, 2004.
Defect Tolerance After the Roadmap
Mahim Mishra and Seth Copen Goldstein. In Proceedings of the 10th International Test Synthesis Workshop (ITSW), March, 2003.
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Mahim Mishra and Seth Copen Goldstein. In Proceedings of the International Test Conference (ITC), 2003, September, 2003.
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Mihai Budiu and Seth Copen Goldstein. In Proceedings of the 1st International ACM/IEEE Symposium on Code Generation and Optimization (CGO 03), pages 216–227, March, 2003.
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Mihai Budiu and Seth Copen Goldstein. In Proceedings of the 12th International Conference on Field Programmable Logic and Applications, pages 853–863, September, 2002.
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Pegasus: An Efficient Intermediate Representation
Mihai Budiu and Seth Copen Goldstein. Carnegie Mellon University Technical Report No. CMU-CS-02-107, pages 20, May, 2002.
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Seth Copen Goldstein and Mihai Budiu. In Proceedings of the 28th International Symposium on Computer Architecture (ISCA), pages 178–189, July, 2001.
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