Heterogeneous Latch-Based Asynchronous Pipelines

 

Asynchronous Circuits and Systems, International Symposium on

Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein

pages 83–92, Los Alamitos, CA, USA

1990

Abstract


download pdf


@inproceedings{venkataramani-async08,
  author = {Venkataramani, Girish and Chelcea, Tiberiu and Goldstein,
     Seth Copen},
  title = {Heterogeneous Latch-Based Asynchronous Pipelines},
  journal = {Asynchronous Circuits and Systems, International
     Symposium on},
  year = {2008},
  issn = {1522-8681},
  pages = {83--92},
  keywords = {Asychronous Circuits},
  doi = {http://doi.ieeecomputersociety.org/10.1109/ASYNC.2008.21},
  publisher = {IEEE Computer Society},
  address = {Los Alamitos, CA, USA},
  abstract = {We present a technique to automatically synthesize
     heterogeneous asynchronous pipelines by combining two different
     latching styles: normally open D-latches for high performance and
     self-resetting D-latches for low power. Theformer is fast but
     results in high power consumption due to data glitches that leak
     through the latch when it is open. The latter is normally closed
     and is opened just before data stabilizes. Thus, it is more
     power-efficient but slower than normally open D-latches. We
     propose a module selection optimization that assigns each
     pipeline stage to one of these two latching styles. This is
     performed by an automated algorithm that uses two types of
     heuristics: (1) it uses the Global Critical Path (GCP), to assign
     D-latches to stages that are sequentially critical, and (2) it
     estimates potential datapath glitching to make SR-latch
     assignment decisions. The algorithm has quadratic-time complexity
     and experiments that apply the algorithm on several media
     processing kernels indicate that, on average, the heterogeneous
     pipelining algorithm achieves higher performance and is more
     energy efficient than either the homogeneous D-latch or SR-latch
     pipeline styles.},
  url = {http://www.cs.cmu.edu/~seth/papers/venkataramani-async08.pdf},
}

Related Papers

Asychronous Circuits
Heterogeneous Latch-Based Asynchronous Pipelines
Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. Asynchronous Circuits and Systems, International Symposium on, pages 83–92, 1990.
Slack Analysis in the System Design Loop
Girish Venkataramani and Seth Copen Goldstein. In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), pages 231–236, Oct 1990.
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Tiberiu Chelcea, Girish Venkataramani, and Seth Copen Goldstein. In Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, pages 117–128, Mar 1990.
Global Critical Path: A Tool for System-Level Timing Analysis
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein. In Proceedings of the 44th ACM/IEEE Design Automation Conference, pages 783–786, Jun 1990.
Operation Chaining Asynchronous Pipelined Circuits
Girish Venkataramani and Seth Copen Goldstein. In ICCAD, Nov 1990.
Self-Resetting Latches for Asynchronous Micro-Pipelines
Tiberiu Chelcea, Girish Venkataramani, and Seth Copen Goldstein. In Proceedings of the 44th ACM/IEEE Design Automation Conference, pages 986–989, Jun 1990.
Hardware Compilation of Application-Specific Memory Access Interconnect
Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, and Seth Copen Goldstein. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 25(5):756–771, 1990.
Leveraging Protocol Knowledge in Slack Matching
Girish Venkataramani and Seth Copen Goldstein. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 1990.
Modeling the Global Critical Path in Concurrent Systems
Girish Venkataramani, Tiberiu Chelcea, Mihai Budiu, and Seth Copen Goldstein. Carnegie Mellon University Technical Report No. CMU-CS-06-144, Aug 1990.
Tartan: Evaluating Spatial Computation for Whole Program Execution
Mahim Mishra, Timothy J Callahan, Tiberiu Chelcea, Girish Venkataramani, Mihai Budiu, and Seth Copen Goldstein. In 12th ACM International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), pages 163–174, Oct 1990.
Adding Faster with Application Specific Early Termination
David Ryan Koes, Tiberiu Chelcea, Charles Onyeama, and Seth Copen Goldstein. Carnegie Mellon University Technical Report No. CMU-CS-05-101, pages 20, May 1990.
SOMA: A Tool for Synthesizing and Optimizing Memory Accesses in ASICs
Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, and Seth Copen Goldstein. In IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS), pages 231–236, Sep 1990.
HLS Support for Unconstrained Memory Accesses
Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. In IEEE 14th International Workshop on Logic Synthesis (IWLS), Jun 1990.
Spatial Computation
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. In International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 14–26, Oct 1990.
Translating ANSI C to Asynchronous Circuits
Mihai Budiu, Girish Venkataramani, Tiberiu Chelcea, and Seth Copen Goldstein. In 10th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC '04), Apr 1990.
C to Asynchronous Dataflow Circuits: An End-to-End Toolflow
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein. In IEEE 13th International Workshop on Logic Synthesis (IWLS), Jun 1990.
Molecules, Gates, Circuits, Computer
Seth Copen Goldstein and Mihai Budiu. In Molecular Nanoelectronics, Jan 1990.


Back to publications list