Pipeline Reconfigurable FPGAs

 

Journal of VLSI Signal Processing Systems

Herman Schmit, Srihari Cadambi, Matthew Moe, and Seth Copen Goldstein

33(4):70–77

Apr 1990

Abstract


download pdf


@article{schmit-jvlsi00,
  author = {Schmit, Herman and Cadambi, Srihari and Moe, Matthew and
     Goldstein, Seth Copen},
  title = {Pipeline Reconfigurable FPGAs},
  journal = {Journal of VLSI Signal Processing Systems},
  volume = {33},
  month = {Apr},
  year = {2000},
  pages = {70-77},
  abstract = {While reconfigurable computing promises to deliver
     incomparable performance, it is still a marginal technology due
     to the high cost of developing and upgrading applications.
     Hardware virtualization can be used to significantly reduce both
     these costs. In this paper we describe the benefits of hardware
     virtualization, and show how it can be achieved using the
     technique of pipeline reconfiguration. The result is PipeRench,
     an architecture that supports robust compilation and provides
     forward compatibility. Our preliminary performance analysis on
     PipeRench predicts that it will outperform commercial FPGAs and
     DSPs in both overall performance and in performance normalized
     for silicon area over a broad range of problem sizes.},
  number = {4},
  url = {http://www.cs.cmu.edu/~seth/papers/schmit-jvlsi00.pdf},
  doi = {},
  also = {chapter in Field-Programmable Custom Computing Technology:
     Architecture, Tools, and Applications},
  keywords = {PipeRench,Reconfigurable Computing},
}

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Pipeline Reconfigurable FPGAs
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Tunable Fault Tolerance for Runtime Reconfigurable Architectures
Steven K. Sinha, Peter M. Kamarchik, and Seth Copen Goldstein. In 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), pages 185–192, Apr 1990.
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
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