Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Mehdi Baradaran Tahoori	Professor Northeastern U ece.neu.edu/faculty/mtahoori		FPGA Testing, VLSI Test Automation, reliability and fault tolerance, test, defect and fault tolerance for molecular and nano-technology, noise issues in deep sub-micron VLSI, CAD, reconfigurable computing dblp
Deependra Talla	System Architect Texas Instruments ece.villanova.edu/~deepu		computer architecture, multimedia and DSP, workload characterization, ASIC and FPGA design dblp
Madhusudhan Talluri	Sunsoft, Sun cs.wisc.edu/~talluri/talluri.html (old)		virtual memory dblp
Andrew S. Tanenbaum	Professor Vrije U., Amsterdam, Netherlands cs.vu.nl/~ast/		distributed systems, compilers, many textbooks dblp
Zhimin Tang	Professor Institute of Computing Technology, Chinese Academy of Sciences ict.ac.cn/chpc/tang		ASIC design, parallel processing, dblp
Olivier Tardieu	Postdoc Columbia U CS www1.cs.columbia.edu/~tardieu		alias analysis, embedded systems dblp
Robert Endre Tarjan	Professor Princeton U, CS cs.princeton.edu/~ret Turing (1986) award		graph algorithms dblp
Valerie E. Taylor	Professor Texas A&M U, CS cs.tamu.edu/people/faculty/taylor		high performance computing, performance analysis and modeling of parallel and distributed applications dblp
Jürgen Teich	Professor U Erlangen-Nuremberg, Germany www12.informatik.uni-erlangen.de/people/teich/index.php		embedded systems, scheduling theory and optimization, massively parallel VLSI architectures dblp
Tim Teitelbaum	Professor Cornell U cs.cornell.edu/Info/People/tt/Tim_Teitelbaum.html		incremental computation, transformational programming, programming environments, language-based editors, compilers, attribute grammars, Ada, synthesizer dblp
Olivier Temam	Professor U Paris Sud, France lri.fr/~temam		microarchitecture, memory locality dblp
Dan Teodosiu	Researcher Microsoft Research		multiprocessors, Scheme, compression dblp
Russell Tessier	Professor U Massachusetts Amherst ecs.umass.edu/ece/tessier		hardware verification, reconfigurable hardware, CAD and logic synthesis dblp
Charles P. Thacker	Microsoft Research Silicon Valley nae.edu/NAE/awardscom.nsf/weblinks/LRAO-5X4TYX?OpenDocument		Firefly, Xerox Alto, Tablet PC, Ethernet, AUTONET dblp
Chandramohan A. Thekkath	Microsoft Research research.microsoft.com/~thekkath		operating systems, distributed systems, networks, interaction architecture/OS dblp
Kevin B. Theobald	Professor U of Delaware capsl.udel.edu/~theobald		multithreaded architectures, branch prediction, EARTH dblp
Michael Theobald	Postdoc Carnegie Mellon U CS www-2.cs.cmu.edu/~theobald		asynchronous circuits, formal verification, CAD, logic and high-level synthesis, BDD and SAT Techniques, embedded and hybrid systems dblp
Lothar Thiele	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~thiele		models/methods/software tools for embedded systems design, array processors, parallel algorithms for signal and image processing, combinatorial optimization, cryptography dblp
Donald E. Thomas	Professor Carnegie Mellon U, ECE ece.cmu.edu/~thomas		hardware/software co-design, Verilog dblp
Carol L. Thompson	Hewlett-Packard		compilers for Itanium dblp
Ken Thompson	Bell Labs, Lucent cm.bell-labs.com/cm/cs/who/ken (old) Turing (1983) award		Unix, Plan 9 dblp
Mithuna S. Thottethodi	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~mithuna		microarchitecture, communication in distributed microarchitectures, systems architecture, interconnection networks dblp
Michael D. Tiemann	Vice President RedHat Inc. redhat.com/about/corporate/team/tiemann.html		g++, Cygnus dblp
Frank Tip	IBM T.J. Watson research.ibm.com/people/t/tip		whole-program optimization of object-oriented applications, program analyis/slicing/understanding/refactoring, compiler optimization dblp
Francisco Tirado	Professor U Complutense de Madrid, Spain dacya.ucm.es/paco		parallel processing for scientific computing, scalability of parallel systems, parallel architectures, processor microarchitecture dblp
Robert Tomasulo	IBM ? Eckert-Mauchly (1997) award		Tomasulo's algorithm (out-of-order execution)
Hiroyuki Tomiyama	Professor Nagoya U, Japan ertl.jp/~tomiyama		system-level design methodologies for system-on-chip, high-level synthesis, compilers for low-power embedded systems, analysis and optimization of real-time software dblp
Karen A. Tomko	Professor U of Cincinatti ece.uc.edu/~ktomko		reconfigurable computing, high performance computing, scientific application performance, graph partitioning, compiler assisted optimization dblp
Linda Torczon	Research scientist Rice U, CS cs.rice.edu/~linda		code generation, interprocedural dataflow analysis, ParaScope dblp
Hwa C. Torng	Professor (emeritus) Cornell U, ECE ee.cornell.edu/people/faculty/torng/htorng.shtml		advanced RISC and superscalar architecture, design of intelligent and broadband telecommunication networks, task scheduling in multi-processors dblp
Josep Torrellas	Professor U of Illinois Urbana-Champaign, CS iacoma.cs.uiuc.edu/~torrella		Polaris, I-ACOMA, FlexRAM dblp
Nur A. Touba	Professor U of Texas, Austin, ECE ece.utexas.edu/~touba		CAD, testing, fault tolerant computing dblp
Dan Truong	Hewlett-Packard irisa.fr/caps/people/truong (old)		software cache optimization, data and instruction layout and prefetching, profile-based optimization dblp
Dean M. Tullsen	Professor UC San Diego www-cse.ucsd.edu/users/tullsen		SMT, speculation, ILP dblp
Gary Scott Tyson	Professor U of Michigan eecs.umich.edu/~tyson		computer architecture, compiler optimization dblp