Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Martín Abadi	Professor U of California at Santa Cruz cse.ucsc.edu/~abadi/home.html		security, programming languages, specification and verification dblp
Tarek S. Abdelrahman	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~tsa		Jasmine compiler, NUMAchine multiprocessor, POW system dblp
Mokhtar Aboelaze	Professor York U, Canada cs.yorku.ca/~aboelaze		omputer networks, mobile networks, computer architecture, special purpose architecture for image processing dblp
Jacob A. Abraham	Professor U of Texas, Austin, ECE cerc.utexas.edu/~jaa		VLSI design and test, formal verification, fault-tolerant computing dblp
Santosh G. Abraham	Sun Microsystems trimaran.org/car_group/santosh_abraham.html (old)		multiprocessor systems, optimizing compilers, performance evaluation, memory hierarchy simulation and design, Cheetah cache simulator, Trimaran, Elcor dblp
Miron Abramovici	Chief Technical Officer DAFCA Inc. bell-labs.com/user/miron (old)		CAD and testing, reconfigurable computing, FPGAs dblp
David Abramson	Professor Monash U, Australia csse.monash.edu.au/~davida		high performance computer systems design, software engineering tools for programming parallel and distributed supercomputers dblp
Shail (Gupta) Aditya	Senior Research Scientist Hewlett-Packard Labs, Compiler and Architecture Group trimaran.org/car_group/shail_aditya.html		PICO, Elcor, Id, parallel Haskell, parallel computing, compilers dblp
Ali-Reza Adl-Tabatabai	Intel MRL www-2.cs.cmu.edu/~ali		compiler optimizations, debugging dblp
Sarita Adve	Professor U of Illinois Urbana-Champaign, CS rsim.cs.uiuc.edu/~sadve		RSIM, memory consistency models dblp
Vikram S. Adve	Professor U of Illinois Urbana-Champaign, CS www-sal.cs.uiuc.edu/~vadve		link- and run-time compilation, POEMS, dHPF, compilers for distributed applications, LLVM dblp
Anant Agarwal	Professor MIT cag.lcs.mit.edu/~agarwal Maurice Wilkes (2001) award		RAW, Alewife, Virtual Wires dblp
Gul Agha	Professor U of Illinois at Urbana-Champaign, CS www-osl.cs.uiuc.edu/people?user=agha		Actors, concurrent programming, formal verification, software engineering, programming languages dblp
Dharma P. Agrawal	Professor U of Cincinnati ececs.uc.edu/~dpa		ad hoc and sensor networks, wireless and mobile networks, scheduling and task migration on NOWs, multithreaded execution of OO programs, parallelization of irregular FORTRAN loops dblp
Vishwani D. Agrawal	Professor Auburn U eng.auburn.edu/~vagrawal		SOC test, low-power VLSI design dblp
Alfred V. Aho	Professor Columbia U, CS cs.columbia.edu/~aho		compilers, AWK dblp
Alexander Aiken	Professor Stanford U, CS theory.stanford.edu/~aiken		type systems, static program analysis and abstract interpretation, constraint resolution algorithms, parallel programming, language design, domain specific languages, end user programming, visualization dblp
Anastassia Ailamaki	Professor Carnegie Mellon U, CS cs.cmu.edu/~natassa		computer architecture, databases dblp
David Al-Dabass	Professor Nottingham Trent U, UK ducati.doc.ntu.ac.uk/uksim/dad/webpage.htm		parallel and neural processing, clusters, parallel performance estimation dblp
David H. Albonesi	Professor Cornell U, ECE csl.cornell.edu/~albonesi		computer architecture, microprocessor design, power-aware microarchitecture, performance evaluation dblp
Nikitas A. Alexandridis	Professor George Washington U seas.gwu.edu/~alexan		advanced computer system architectures, high performance processors, parallel and distributed processing, computer vision and image processing/transmission, software prototyping for parallel systems & algorithms, heterogeneous computing dblp
Virgílio A. F. Almeida	Professor U Federal de Minas Gerais, Brazil dcc.ufmg.br/~virgilio		computing systems performance analysis and modeling, e-commerce dblp
Bowen Alpern	IBM T. J. Watson		Jalapeno (Java VM), SSA, theoretical models of hierarchical memory and parallelism, distributed and parallel computing, computational linear algebra dblp
Erik R. Altman	IBM T. J. Watson		DAISY, binary translation, software pipelining dblp
Rajeev Alur	Professor U of Pennsylvania cis.upenn.edu/~alur		design tools for embedded software, formal modeling and verification of reactive systems, model checking, hybrid systems, distributed computing, logic and automata theory dblp
Saman P. Amarasinghe	Professor MIT cag.lcs.mit.edu/~saman		compiler optimizations, computer architectures, software engineering, parallel computing dblp
Gene M. Amdahl	Retired chairman Commercial Data Servers Inc actscorp.com/acts/amdahl.htm Eckert-Mauchly (1987) award		pipelining, instruction look-ahead, cache dblp
Henrik Reif Andersen	Professor IT University of Copenhagen, Denmark itu.dk/people/hra		verification of concurrent and embedded systems, model checking, modal mu-calculus, models of concurrent systems, configuration problems and configuration software, implementation of embedded systems dblp
Tom Anderson	Professor U of Washington Seattle, CS cs.washington.edu/homes/tom		Internet, operating systems, scheduler activations dblp
David Andrews	Professor U of Kansas ittc.ku.edu/~dandrews		real time distributed, embedded systems, computer architecture dblp
Andrew W. Appel	Professor Princeton U cs.princeton.edu/~appel		compilers, functional programming languages dblp
James R. Armstrong	Professor Virginia Tech, EE ecpe.vt.edu/faculty/armstrong.html		modeling with hardware description languages, high level testing dblp
Mark G. Arnold	Professor Lehigh U cse.lehigh.edu/~marnold		computer architecture and arithmetic, hardware description languages dblp
Arvind	Professor MIT csg.lcs.mit.edu/Users/arvind		term-rewriting systems, dynamic dataflow, Id dblp
Krste Asanovic	Professor MIT cag.lcs.mit.edu/~krste		T0 vector microprocessor, low power, neural network implementations dblp
John Vincent Atanasoff	Professor (deceased) Iowa State U, CS cs.iastate.edu/jva/jva-archive.shtml		first digital computer
Peter M. Athanas	Professor Virginia Tech, EE ee.vt.edu/~athanas		computer architecture, VLSI, custom computing machines, parallel processing, hardware/software codesign, high-level synthesis, rapid prototyping of digital systems dblp
Darren C. Atkinson	Professor Santa Clara U cse.scu.edu/~atkinson		software engineering, compilers dblp
David I. August	Professor Princeton U, CS cs.princeton.edu/~august		compilers for predicated architectures dblp
Todd M. Austin	Professor U of Michigan eecs.umich.edu/~taustin		SimpleScalar, Diva (Dynamic Verification), microarchitecture design, low power computing, compiler design, computer system simulation and validation, performance analysis tools and techniques dblp
Eduard Ayguade	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/eduard		parallelizing compilers, OpenMP, data placement optimization, parallel computing in Java, ILP dblp
James H. Aylor	Professor U of Virginia, EE ee.virginia.edu/profile.php?ID=2		system-level modeling, concurrent error detection, automatic test pattern generation, hardware description languages, VLSI system design dblp
Adnan Aziz	Professor U of Texas, Austin, ECE ece.utexas.edu/~adnan		design and verification of digital IC dblp
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Bevan M. Baas	Professor UC Davis ECE ece.ucdavis.edu/~bbaas/		processor architecture, VLSI design, fast Fourier transform processors, low power CMOS
John Backus	computerhistory.org/events/hall_of_fellows/backus/ Turing (1977) award		FORTRAN, Backus-Naur form dblp
David F. Bacon	Researcher IBM T. J. Watson research.ibm.com/people/d/dfb/		design and implementation of programming languages, concurrent systems dblp
Wael M. Badawy	Professor U of Calgary, Canada badawy.ca		architectures for image and video processing, system on a chip dblp
Scott B. Baden	Professor UC San Diego, CS cs.ucsd.edu/users/baden		high performance and scientific computation, application-specific programming models and optimization strategies, KeLP dblp
Jean-Loup Baer	Professor U of Washington Seattle, CS cs.washington.edu/homes/baer		caches, computer architecture, programmable network interfaces dblp
Nader Bagherzadeh	Professor UC Irvine eng.uci.edu/comp.arch/nader.html		MorphoSys, multithreaded architectures, processor architecture dblp
R. Iris Bahar	Professor Brown U, ECE lems.brown.edu/iris.html		computer architecture, low-power design, CAD, nanosystem design dblp
Vasanth Bala	IBM research		parallel computation, Dynamo, dynamic optimization dblp
Thomas Ball	Microsoft Research, Software Productivity Tools research.microsoft.com/~tball		formal methods for programs dblp
Prithviraj Banerjee	Professor Northwestern U, ECE ece.nwu.edu/~banerjee		parallel algorithms for VLSI design automation, distributed memory parallel compilers, compilers for adaptive computing, PARADIGM, ProperCAD, MATCH dblp
Cristina Barrado	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/cristina		automatic parallelization dblp
Luiz André Barroso	Google barroso.org		server workloads, SimOS-Alpha dblp
Rajeev Barua	Professor U of Maryland, ECE ece.umd.edu/~barua		MAPS (Raw compiler), modulo unrolling dblp
Forest Baskett	Venture Partner New Enterprise Associates nea.com/Partners/Bios/Menlo/FBaskettBio		MIPS, SUN, DEC WRL founder dblp
Kenneth E. Batcher	Professor Kent State U, CS cs.kent.edu/~batcher Eckert-Mauchly (1990) award		parallel computers, interconnection networks dblp
Jürgen Becker	Professor U of Karslruhe www-itiv.etec.uni-karlsruhe.de/opencms/opencms/de/institute/staff/becker.html		hardware/software codesign, hardware synthesis, systems-on-a-chip dblp
Robert C. Bedichek	Transmeta Corp. bedichek.org/robert		Alewife, Meerkat, multicomputers dblp
Peter A. Beerel	Professor U of Southern California jungfrau.usc.edu/beerel.html		CAD, mixed asynchronous/synchronous VLSI design dblp
Richard A. Belgard	Consultant members.aol.com/richb89600		computer architecture
Gordon Bell	senior researcher Microsoft Bay Area Research Center research.microsoft.com/users/GBell Eckert-Mauchly (1982) award		minicomputers, timeshring, hardware description languages dblp
Luca Benini	Professor U of Bologna, Italy www-micrel.deis.unibo.it/~benini		computer-aided design of digital circuits, low-power applications, design of portable systems dblp
Siegfried Benkner	Professor U of Vienna, Austria par.univie.ac.at/~sigi		ADVANCE, AURORA, HPF+ dblp
Steve Bennett	Intel, Hillsboro intel.com/research/people/bios/bennett_s.htm		SimpleScalar, trace cache, multiscalar dblp
Alan D. Berenbaum	Agere Systems cm.bell-labs.com/cm/cs/who/adb		computer architecture, architectural support for high-speed networking, VLSI design dblp
Emery D. Berger	Professor U of Massachusetts Amherst, CS cs.umass.edu/~emery		garbage collection, virtual memory management, locality-preserving data structures, compilers for high-level optimization and error detection dblp
Neil W. Bergmann	Professor U of Queensland, Brisbane, Australia itee.uq.edu.au/~bergmann		reconfigurable computing, embedded systems infrastructure for ubiquitous computing dblp
Kees van Berkel	Philips Research, Netherlands research.philips.com/profile/people/fellows/berkel.html		asynchronous circuits, VLSI design dblp
David Bernstein	Department Manager Systems and Software, IBM Research Israel		code scheduling, optimizing compilers dblp
Gerard Berry	Professor Ecole des Mines, Paris, France www-sop.inria.fr/meije/personnel/Gerard.Berry.html		programming languages design/semantics/implementation, reactive and real-time programming, synchronous circuit design and synthesis, automatic verification of FSM, lambda calculus and its models dblp
Vaughn Betz	Altera Corp. eecg.toronto.edu/~vaughn (old)		FPGAs, CAD for FPGAS, computer architecture, VLSI design, VPR dblp
Dileep Bhandarkar	Director of Enterprise Architecture Lab Intel intel.com/pressroom/kits/bios/dbhandarkar.htm		VAX, Prism, MIPS, Alpha, memories, computer architecture dblp
Shuvra S. Bhattacharyya	Professor U of Maryland, ECE ece.umd.edu/~ssb		architectures and CAD for embedded systems, hardware/software co-design for signal/image/video processing dblp
Laxmi N. Bhuyan	Professor UC Riverside, CS cs.ucr.edu/~bhuyan		computer architecture, performance evaluation, parallel and distributed systems, interconnection networks, fault tolerant computing dblp
Ricardo Bianchini	Professor Rutgers U, CS cs.rutgers.edu/~ricardob		parallel/distributed and cluster computing, techniques for optimizing power and energy, new I/O architectures, Internet-related technologies dblp
Armin Biere	Professor ETH Zurich, Switzerland inf.ethz.ch/personal/biere		model checking, hardware verification dblp
Aart J. C. Bik	Intel liacs.nl/home/ajcbik		compilers for scientific computing, Java compilation, automatic vectorization dblp
Angelos Bilas	Professor U of Crete, Greece wwww.ics.forth.gr/~bilas		parallel architectures, programming paradigms, parallel applications, interconnection networks, block-level storage subsystems, performance analysis and evaluation, distributed systems dblp
Benjamin J. Bishop	Professor U of Scranton, CS cs.uofs.edu/~bishop		multimedia systems, computer graphics, processor architecture, VLSI design, low-power electronics, MGAP-II, SPARTA dblp
David T. Blaauw	Professor U of Michigan at Ann Arbor eecs.umich.edu/cgi-bin/fac/facsearchform.cgi?blaauw+		circuit analysis, computer-aided design, high performance design dblp
Stephen M. Blackburn	Professor Australian National U, Australia cs.anu.edu.au/~Steve.Blackburn		programming languages, dynamic cooperative performance optimization Java, transactional object storage, image processing dblp
R. D. (Shawn) Blanton	Professor Carnegie Mellon U, ECE ece.cmu.edu/~blanton		design and test of VLSI, fault-tolerant computing, computer architecture dblp
Guy E. Blelloch	Professor Carnegie Mellon U, CS cs.cmu.edu/~guyb		thread scheduling, parallel algorithms, NESL language, parallel computing dblp
Matthias Blume	Professor Toyota Technical Institute, Chicago people.cs.uchicago.edu/~blume		design and implementation of high-level programming languages, SML/NJ dblp
Matthias A. Blumrich	IBM Research cs.princeton.edu/~mb (old)		SHRIMP, shared memory multiprocessing dblp
Arndt Bode	Professor Technische U Muenchen, Germany wwwbode.cs.tum.edu/~bode		parallel and distributed architectures/applications, programming environments and tools dblp
Rastislav Bodík	Professor UC Berkeley cs.berkeley.edu/~bodik		critical path, compilers, computer architecture dblp
François Bodin	Researcher IRISA, France irisa.fr/caps/people/bodin/index_fr.htm		program optimizations, HPC programming environments, compilers, ILP, parallel computers dblp
Hans-Juergen Boehm	Hewlett-Packard Labs hpl.hp.com/personal/Hans_Boehm/		Boehm-Weiser garbage collector, gcj, multiprocessor synchronization, constructive real arithmetic dblp
Taisuke Boku	Professor U of Tsukuba, Japan arch.is.tsukuba.ac.jp/~taisuke/index-e.html		network topology, data transfer methods for HPC on MPPs dblp
Shekhar Y. Borkar	Director of Circuit Research Intel intel.com/research/people/bios/borkar_s.htm		8051 microcontrollers, iWarp, high-speed signaling for supercomputers dblp
Pradip Bose	Research Staff Member IBM T. J. Watson research.ibm.com/people/b/bose		high-performance computer architectures, CAD, performance evaluation, performance verification, parallel processing, compilers, VLSI testing and verification dblp
Luc Bougé	Professor IRISA/ENS Cachan, Bretagne, France ens-lyon.fr/~bouge		semantics of languages for parallel programming, cluster computing dblp
Donald W. Bouldin	Professor U of Tennessee at Knoxville microsys6.engr.utk.edu/ece/bouldin_home.html		microelectronic systems design, adaptive computing systems, VLSI, ASICs, FPGAs, MCMs, synthesis dblp
Chandrasekhar Boyapati	Professor U of Michigan eecs.umich.edu/~bchandra		software reliability, program analysis dblp
Robert S. Boyer	Professor U of Texas, Austin, CS cs.utexas.edu/users/boyer		theorem prooving, Maxima (Macsyma clone), Boyer-Moore theorem prover, hardware verification dblp
Robert K. Brayton	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~brayton		analysis of nonlinear networks, electrical simulation and optimization of circuits, combinational and sequential logic synthesis, asynchronous synthesis, formal verification dblp
Scott E. Breach	Hewlett-Packard cs.wisc.edu/~breach (old)		multiscalar processors dblp
Gordon J. Brebner	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/gordon		flexible architecture and networking dblp
Mauricio Breternitz Jr.	Intel MRL intel.com/research/people/bios/breternitz_m.htm		parallelizing compilers multiprocessors and VLIW, binary translation, on IP telephony, parallelizing database servers dblp
Melvin A. Breuer	Professor U of Southern California poisson.usc.edu/Breuer.html		CAD, design-for-test and built-in self-test, VLSI circuits dblp
Faye A. Briggs	director of chipset architecture Intel Enterprise Products Group		computer architecture, parallel processing dblp
Robert W. Brodersen	Professor UC Berkeley, ECE bwrc.eecs.berkeley.edu/People/Faculty/rb		low power design, wireless communications, CAD tools dblp
Stephen D. Brookes	Professor Carnegie Mellon U, CS csd.cs.cmu.edu/research/faculty_research/brookes.html		semantics of programming languages, trace semantics dblp
David Brooks	Professor Harvard U eecs.harvard.edu/~dbrooks		interaction architecture/software/hardware, power dissipation and chip cooling modelling, Wattch dblp
Frederick P. Brooks Jr.	Professor U of North Carolina, CS cs.unc.edu/~brooks Turing (1999) award, von Neumann medal (1993), National Medal of Technology (1985), Allen Newell (1994) award, Eckert-Mauchly (2004) award		3D interactive computer graphics, human-computer interaction, virtual worlds, molecular graphics, IBM S/360, STRETCH, The Mythical Man-Month dblp
Mats Brorsson	Professor Royal Institute of Technology, Stockholm, Sweden it.kth.se/~matsbror		energy aware architectures, shared address space multiprocessors, programming models for parallel programs, software DSM dblp
Angela Demke Brown	Professor U of Toronto, CS, Canada cs.toronto.edu/~demke		compiler-guided resource management, run-time adaptation, operating systems, compiler optimization, parallel and distributed systems dblp
Donna J. Brown	Professor U of Illinois at Urbana-Champaign, ECE wocket.csl.uiuc.edu/~djb		VLSI layout, combinatorial algorithms, parallel and distributed algorithms and architecture, Web-based instruction, Mallard dblp
Richard B. Brown	Dean, College of Engineering U of Utah coe.utah.edu/brown		IC design (VLSI), solid-state chemical sensors, MEMS, mixed-signal circuits, high-performance, radiation-hard and low-power microprocessors, CMOS/SOI/GaAs dblp
Stephen Dean Brown	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~brown		FPGAs, CAD, place and route dblp
Erik Brunvand	Professor U of Utah, CS cs.utah.edu/~elb/home.html		computer architecture, VLSI systems, self-timed and asynchronous systems dblp
Randal E. Bryant	Professor Carnegie Mellon U, CS cs.cmu.edu/~bryant		Binary Decision Diagrams (BDD), formal verification, model checking dblp
Mihai Budiu	Microsoft Research cs.cmu.edu/~mihaib (old)		reconfigurable hardware, optimizing compilers, spatial computation dblp
Duncan A. Buell	Professor U of South Carolina cse.sc.edu/~buell		Splash 2 reconfigurable system, numeric computations, parallel algorithms and architectures, computational number theory dblp
Doug Burger	Professor U of Texas, Austin, CS cs.utexas.edu/users/dburger		SimpleScalar, Datascalar, memory systems dblp
Neil Burgess	Professor Cardiff U, UK engin.cf.ac.uk/whoswho/profile.asp?RecordNo=138		computer arithmetic, digital signal processing, hardware support for DSP dblp
Wayne P. Burleson	Professor U of Massachusetts Amherst ECE ecs.umass.edu/ece/vspgroup/burleson.html		VLSI signal processing, on-chip interconnects, reconfigurable computing dblp
Martin Burtscher	Professor Cornell U, ECE csl.cornell.edu/~burtscher		high-performance microprocessor architecture, ILP, compiler optimizations, value prediction, data compression, latency-reduction techniques dblp
Rajkumar Buyya	Professor Monash U, Australia buyya.com		computer architecture, operating systems, compilers, parallel / distributed / cluster / grid / peer-to-peer computing dblp
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George Z. N. Cai	Engineering manager Intel Design Center, Texas		power modeling and management, microprocessor design and implementation dblp
Brad Calder	Professor UC San Diego www-cse.ucsd.edu/users/calder		prediction, mobile code, PSSA dblp
Timothy J. Callahan	post-doc Carnegie Mellon U, CS www-2.cs.cmu.edu/~tcal		GARP, reconfigurable hardware compilation, system-on-a-chip design automation, hardware/software codesign dblp
João M. P. Cardoso	Professor U of Algarve, Portugal w3.ualg.pt/~jmcardo		reconfigurable computing, high-level synthesis for FPGAs, design automation for embedded systems dblp
Douglas M. Carmean	principal engineer/architect Intel Desktop Products, Oregon		IA-32, Pentium, Pentium 4 dblp
Steven M. Carr	Professor Michigan Technological U, CS cs.mtu.edu/~carr		high-level optimization for DSP, compilers-computer architecture interaction, concurrent computing dblp
John B. Carter	Professor U of Utah, CS cs.utah.edu/~retrac		operating systems, parallel and distributed computing, multiprocessor computer architecture, memory system design, Munin dblp
Lori Carter	Professor Point Loma Nazarene U, San Diego mcs.ptloma.edu/Carter		computer architecture, compiler optimizations, predicated execution, compilation for IA64 dblp
Nicholas P. Carter	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~npcarter		reconfigurable logic, computing using non-silicon dblp
Calin Cascaval	IBM T. J. Watson polaris.cs.uiuc.edu/~cascaval (old)		parallel compilers, parallel and distributed computing, object oriented compilers and methodologies dblp
Steve Casselman	Virtual Computer Corp		reconfigurable computing, search engines dblp
Gregory J. Chaitin	IBM T. J. Watson cs.umaine.edu/~chaitin		register allocation, algorithmic information theory dblp
Craig Chambers	Professor U of Washington Seattle, CS cs.washington.edu/homes/chambers		SPIN, dynamic compilation, Vortex, Cecil dblp
Fay Chang	Google cs.cmu.edu/~fwc (old)		Speculative prefetching for disk data, distributed filesystems dblp
J. Morris Chang	Professor Iowa State U, EE vulcan.ee.iastate.edu/~morris		wireless network, computer architecture, object-oriented programming languages, memory management, hardware description languages, internet architecture dblp
Craig M. Chase	Professor U of Texas, Austin, ECE ece.utexas.edu/~chase		parallel architectures and algorithms dblp
Siddhartha Chatterjee	Professor U of North Carolina, CS cs.unc.edu/~sc		cache-conscious algorithms, data parallelism dblp
Tiberiu Chelcea	postdoc Carnegie Mellon U, CS cs.cmu.edu/~tibi		asynchronous circuits dblp
Peter M. Chen	Professor U of Michigan eecs.umich.edu/~pmchen		RIO, ARMADA, fault tolerance, disk systems dblp
Tien-Fu Chen	Professor National Chung Cheng U, China cs.ccu.edu.tw/~chen		computer architecture, SOC design, embedded systems dblp
Fu-Chiung John Cheng	Professor Tatung U, Taiwan cse.ttu.edu.tw/~cheng		Systems-on-a-chip, hardware-software codesign, CAD tools, asynchronous logic, FPGAs, Java-enabled embedded systems, real-time OS, expert database systems dblp
Perry Cheng	IBM T.J. Watson research.ibm.com/people/p/perryche		garbage collection, type-directed compilation dblp
David R. Cheriton	Professor Stanford U www-dsg.stanford.edu/DavidCheriton.html		distributed systems, high performance networks, operating systems, distributed interactive simulation, object-oriented design techniques dblp
Peter Y. K. Cheung	Professor Imperial College, London, UK ee.ic.ac.uk/pcheung		reconfigurable computing, hardware/software codesign, CAD, Digital and Asynchronous Systems, VLSI architecture for signal processing, mixed signal designs dblp
Men-Chow Chiang	IBM Server Group		memory systems for multiprocessors dblp
Donald M. Chiarulli	Professor U of Pittsburgh, EE cs.pitt.edu/~don		chip level optoelectronic interconnections, optical-electronic-mechanical multi-domain CAD, optical memory systems, robotics, SOC voice based interfaces dblp
Andrew A. Chien	Professor UC San Diego www-csag.ucsd.edu/individual/achien/achien.html		Agile Distributed Objects, High Performance Virtual Machines (HPVM), Illinois Concert Project, QoS management dblp
Bruce R. Childers	Professor U of Pittsburgh, CS cs.pitt.edu/~childers		automatic design of application-specific processors, custom VLIW/systolic architectures, low-power embedded processors, computer architecture, compilers and software development tools dblp
Trishul M. Chilimbi	Microsoft Research research.microsoft.com/~trishulc		optimizations for caching dblp
Giovanni Chiola	Professor U di Genova, Italy disi.unige.it/person/ChiolaG		active messages (GAMMA), distributed databases dblp
Derek Chiou	Professor U of Texas at Austin ECE ece.utexas.edu/~derek		simulators, sequential and parallel computer architectures, router architecture, dataflow machines, StarT dblp
Jong-Deok Choi	IBM Research T. J. Watson research.ibm.com/people/j/jdchoi		programming languages, compiler optimizations, software engineering dblp
Kiyoung Choi	Professor Seoul National U, Korea poppy.snu.ac.kr/~kchoi/kchoi.html		VLSI design, CAD, hardware-software codesign, high-level synthesis, low-power system design dblp
Frederic T. Chong	Professor UC Davis, CS american.cs.ucdavis.edu:80/~chong		Active Pages dblp
Pai H. Chou	Professor UC Irvine ece.uci.edu/~chou		IMPACCT, embedded systems, low power design dblp
Alok N. Choudhary	Professor Northwestern U ECE ece.northwestern.edu/~choudhar		compilers and runtime systems for high-performance embedded/adaptive/power-aware systems, high-performance databases, parallel and high-performance storage and I/O systems dblp
Fred C. Chow	Pathscale, Inc.		optimizing compilers dblp
Paul Chow	Professor U of Toronto, EE, Canada eecg.toronto.edu/~pc		FPGAs, OneChip, Transmogrifier-2 dblp
Giuseppe Ciaccio	Professor U di Genova, Italy disi.unige.it/person/CiaccioG		clusters of PCs, operating systems, parallel processing, parallel computer architecture dblp
Michal Cierniak	researcher Intel Microprocessor Research Labs, Programming Systems Lab intel.com/research/mrl/people/cierniak_m.htm		virtual machines, runtime systems, just-in-time compilation, high-performance compiler optimizations dblp
Marcelo H. Cintra	Professor U of Edinburgh, UK dcs.ed.ac.uk/home/mc		computer architectures, parallel and high-performance computing, scientific computing dblp
Douglas W. Clark	Professor Princeton U, CS cs.princeton.edu/~doug		processor architecture and organization, performance measurement and analysis, computer architecture, Display Wall dblp
Wesley A. Clark	Clark, Rockoff and Associates Eckert-Mauchly (1981) award		design of early computers, TX-0, TX-2 dblp
Edmund M. Clarke	Professor Carnegie Mellon U, CS cs.cmu.edu/~emc		formal verification, model checking dblp
John G. Cleary	Professor U of Waikato, New Zealand cs.waikato.ac.nz/Staff/john-g.-cleary.html		parallel and distributed systems, TimeWarp, compression, logic programming dblp
Cliff Click	Motorola crpc.rice.edu/MSCP/cliff.html (old)		compiler optimizations, intermediate program representations dblp
John Cocke	(deceased) IBM T. J. Watson Eckert-Mauchly (1985) award, Turing (1987) award		optimizing compilers, RISC processors dblp
Robert S. Cohn	Intel		Alpha compilers, profile-feedback compilation, Spike, code layout in Unix OM dblp
Michele Colajanni	Professor U di Modena, Italy traianus.ce.uniroma2.it/people/colajanni.html		distributed parallel computing, distributed web servers, parallel scientific computing, fault-tolerance, interconnection networks, performance analysis and simulation dblp
Osvaldo Colavin	ST Microelectronics		architectural support for multimedia dblp
Jean-Francois Collard	Intel prism.uvsq.fr/~jfcollar (old)		automatic parallelization, optimizing compilers dblp
Robert P. Colwell	Colwell and Associates, Inc. Eckert-Mauchly (2005) award		Pentium Pro, Multiflow dblp
Hubert Comon-Lundh	Professeur Ecole Normale Superieure de Cachan, France lsv.ens-cachan.fr/~comon/		term rewriting, symbolic constraint solving, tree automata techniques, verification of infinite state systems, cryptographic protocols dblp
Katherine Compton	Professor U of Wisconsin-Madison ECE ece.wisc.edu/~kati/		reconfigurable computing dblp
Jason Cong	Professor U of California at Los Angeles, CS ballade.cs.ucla.edu/~cong		hardware synthesis, giga-scale system-on-a-chip, FPGAs, large-scale CAD dblp
Daniel A. Connors	Professor U of Colorado, CS cs.colorado.edu/~dconnors		high performance computer systems, run-time optimization architectures, embedded systems, optimizing compilers, operating systems dblp
Charles Consel	Professor ENSEIRB/LaBRI/INRIA Bordeaux, France compose.labri.u-bordeaux.fr/people/consel		programming languages, program analysis and transformation, software engineering, operating systems dblp
Thomas M. Conte	Professor North Carolina State U, ECE tconte.org		compiler design, advanced microarchitectures, VLIW/IA-64 compilers dblp
Lynn Conway	Professor (emeritus) U of Michigan ai.eecs.umich.edu/people/conway/conway.html		VLSI, robotics/AI dblp
Stephen A. Cook	Professor U of Toronto, CS, Canada cs.toronto.edu/~sacook Turing (1982) award		NP-completeness, computational complexity, logic dblp
William R. Cook	Professor U of Texas at Austin, CS cs.utexas.edu/users/wcook		programming languages, mixins, type theory, object-oriented programming, interfacing languages and databases, software engineering, web-based information systems, information security dblp
Keith D. Cooper	Professor Rice U, CS cs.rice.edu/~keith		Rn, ParaScope, low-level code optimization, code generation, GrDAS dblp
Lee D. Coraor	Professor Penn State U cse.psu.edu/gradbroc/faculty/coraor.html		FPGAs, SmartDIMM (computing in memory) dblp
Henk Corporaal	Professor Technische U Eindhoven, Netherlands ics.ele.tue.nl/~heco		automatic synthesis of application specific processors, very large scale distributed embedded DSP systems dblp
Jordi Cortadella	Professor U Politecnica de Catalunya, Spain lsi.upc.es/~jordic		synthesis, analysis and verification of concurrent systems, asynchronous systems, logic synthesis, Petrify dblp
Michel Cosnard	Professor/director INRIA inria.org/presse/cvmc.en.html		parallel algorithms and architectures, algorithm complexity, automata theory and neural networks, discrete dynamical systems dblp
Patrick Cousot	Professor Ecole Normale Superieure Paris, France di.ens.fr/~cousot		abstract interpretation, semantics dblp
Radhia Cousot	Research Director Ecole Polytechnique, France di.ens.fr/~cousot		abstract interpretation, semantics, proofs dblp
Alan L. Cox	Professor Rice U, CS cs.rice.edu/~alc		TreadMarks, FASTLINK dblp
Harvey G. Cragon	Professor (emeritus) U of Texas, Austin, ECE ece.utexas.edu/ece/people/profs/Cragon.html Eckert-Mauchly (1986) award		first integrated circuit computer, first TTL computer dblp
Karl Crary	Professor Carnegie Mellon U, CS cs.cmu.edu/~crary		type-oriented compilation strategies, type-based certification of mobile code, high-level programming language design dblp
John Crawford	Director of McKinley Architecture Intel Architecture Group, Enterprise Platforms Group intel.com/pressroom/kits/bios/crawford.htm Eckert-Mauchly (1995) award		IA-64, 80386, Pentium dblp
Seymour Cray	(deceased) cgl.ucsf.edu/home/tef/cray/tribute.html Eckert-Mauchly (1989) award		supercomputers
Stefano Crespi-Reghizzi	Professor Politecnico di Milano, Italy elet.polimi.it/people/crespi		formal languages and automata, compiler optimization and parallelization, programming languages, man-machine interfaces dblp
Darren C. Cronquist	Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/darren-cronquist-page.html		architectures/compilers/languages for embedded applications, RaPiD (reconfigurable hardware), PICO dblp
Mark Crovella	Professor Boston U, CS cs-www.bu.edu/faculty/crovella		performance evaluation of parallel and networked computers, measuring and characterizing the web dblp
David E. Culler	Professor UC Berkeley, CS cs.berkeley.edu/~culler		Active Messages, Threaded Abstract Machine, parallel architectures dblp
Walling R. Cyre	Professor Virginia Tech, EE ecpe.vt.edu/faculty/cyre.html		automatic design, requirements analysis, natural language understanding, automatic modeling, high-level synthesis, design representation dblp
Ronald K. Cytron	Professor Washington U in St. Louis, CS cs.wustl.edu/~cytron		SSA, compilers, continuous compilers, packet filtering, secure voting dblp
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Ole-Johan Dahl	(deceased) Oslo U, Norway ifi.uio.no/~olejohan Turing (2001) award, von Neumann Medal (2001)		Simula, type theory, object-oriented programming dblp
Fredrik Dahlgren	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~dahlgren		high-performance multiprocessors, multiprocessors for telecom systems dblp
William J. Dally	Professor Stanford U csl.stanford.edu/~billd Maurice Wilkes (2000) award		Imagine, J-machine, the reliable router, high-speed interconnection networks dblp
Marco Danelutto	Professor U of Pisa, Italy di.unipi.it/~marcod		parallel programming with skeletons, P3L, parallel functional, ocamlp3l, (massively) parallel architectures, ILP, Linux clusters dblp
Alain Darte	Researcher CNRS ens-lyon.fr/~darte/index-us.html		automatic parallelization, HPF, Nestor, scheduling, systolic arrays dblp
Chitaranjan R. Das	Professor Pennsylvania State U cse.psu.edu/~das		computer architecture, parallel and distributed computing, design and analysis of routing algorithms, processor management in multiprocessors, performance evaluation and fault-tolerant computing dblp
Manuvir Das	Microsoft Research research.microsoft.com/users/Manuvir/homepage.html		static program analysis, application to compilers/error detection/program verification dblp
Aravind Dasu	Professor Utah State U ece.usu.edu/ece/faculty_staff/profile.php?id=229		reconfigurable computing for media and scientific computing dblp
Edward S. Davidson	Professor (emeritus) U of Michigan eecs.umich.edu/~davidson Eckert-Mauchly (2000) award		computer architecture, supercomputing, parallel and pipelined computers, performance modeling and optimization, application code, assessment and tuning, VLSI systems, memory organization and management, CAD dblp
Jack W. Davidson	Professor U of Virginia, CS cs.virginia.edu/~jwd		zephyr, high-performance embedded applications, dynamic optimization for power dblp
Al Davis	Professor U of Utah, CS cs.utah.edu/~ald		parallel computer architecture, adaptive memory systems, asynchronous circuits and systems dblp
Nathaniel J. Davis	Professor Virginia Tech, EE ecpe.vt.edu/faculty/davisnj.html		advanced computer architectures, parallel processing, interconnection networks, computer networks, computer system simulation and performance modeling, embedded microprocessor systems dblp
Koen De Bosschere	Professor Ghent U, Belgium elis.ugent.be/~kdb		debugging of parallel programs, Java technology, link-time optimization, computer architecture dblp
Bjorn De Sutter	postdoc Gent U, Belgium elis.ugent.be/~brdsutte		binary rewriting, embedded software optimization, low-power optimization, reconfigurable computing, software protection techniques, computer architecture, program compaction dblp
Alexander G. Dean	Professor North Carolina State U cesr.ncsu.edu/agdean		computer architecture and compilation techniques for embedded systems, software thread integration dblp
Saumya K. Debray	Professor U of Arizona cs.arizona.edu/people/debray		programming languages and compilers, binary rewriting and link-time code optimization, code compression dblp
James C. Dehnert	Transmeta		compilers, Standard Template Library, Cydra 5 dblp
André DeHon	Professor Caltech U, CS cs.caltech.edu/~andre		reconfigurable hardware, DPGA, MATRIX dblp
José G. Delgado-Frias	Professor Washington State U eecs.wsu.edu/~jdelgado		VLSI microarchitectures, routers, immunity-/genetic-/neural network-based computing dblp
Robert DeLine	Microsoft Research research.microsoft.com/users/rdeline		user interfaces, software engineering, type theory, Vault dblp
James Demmel	Professor UC Berkeley, CS cs.berkeley.edu/~demmel		LAPACK, ScaLAPACK, linear systems, numerical methods dblp
Jack B. Dennis	Professor (emeritus) MIT lcs.mit.edu/people/bioprint.php3?Record_ID=26 Eckert-Mauchly (1984) award		dataflow computers, stream processors dblp
Alvin M. Despain	Professor U of Southern California isi.edu/acal/people/despain.html		computer architecture, multiprocessor systems, logic programming, quantum computation, design automation dblp
Dave Detlefs	Sun Labs East research.sun.com/people/detlefs		Extended Static Checker, Simplify theorem prover, garbage collection dblp
Srinivas Devadas	Professor MIT glenfiddich.lcs.mit.edu/~devadas		VLSI design, CAD, computer architecture, hardware validation, architectural synthesis for programmable processors, smart caches, security problems in pervasive computing dblp
Keith Diefendorff	Apple		Apple/PowerPC, AMD K6, Motorola 88110 dblp
Oliver Frank Diessel	Lecturer U of New South Wales, Sydney, Australia cse.unsw.edu.au/~odiessel		design and management of reconfigurable computer systems and applications dblp
Henry G. (Hank) Dietz	Professor U of Kentucky aggregate.org/hankd		parallel processing, compilers, hardware architectures and networking, operating systems, digital imaging dblp
Edsger Wybe Dijkstra	(deceased) U of Texas, Austin, CS cs.utexas.edu/users/UTCS/report/1997/dijkstra.html Turing (1972) award		formal methods dblp
David L. Dill	Professor Stanford U verify.stanford.edu/dill		hardware verification dblp
Chen Ding	Professor U of Rochester, CS cs.rochester.edu/u/cding		compiler enhancement of global cache reuse, dynamic program analysis and transformation, Smooth, performance tuning and prediction for memory hierarchy dblp
Pedro Diniz	Professor U of Southern California Information Sciences Institute isi.edu/~pedro		commutativity analysis, parallelizing compilers, program analysis, parallel and distributed computing, configurable computing dblp
Stephen W. Director	Dean, College of Engineering U of Michigan engin.umich.edu/director		design process, statistical VLSI design dblp
David R. Ditzel	CTO Transmeta Corp.		SPARC, Transmeta dblp
Amer Diwan	Professor U of Colorado, Boulder, CS cs.colorado.edu/~diwan		compiler analyses and optimizations, memory management, memory system performance, power-aware computing, software engineering/visualization tools dblp
Alex Doboli	Professor State U of New York at Stony Brook ece.sunysb.edu/~adoboli		CAD for embedded systems and Systems-on-Chip, specification/modeling/synthesis of heterogeneous-domain systems dblp
Apostolos Dollas	Professor Technical U of Crete mhl.tuc.gr/PERSONEL/cvs/Dollas_alt2.html		rapid system prototyping, computer architecture, reconfigurable computing, embedded systems, application specific high-performance digital systems dblp
Lorenzo Donatiello	Professor U of Bologna, Italy cs.unibo.it/~donat		performance models of computer and communication systems, performability models of fault-tolerant systems, wireless networks, parallel and distributed simulation dblp
Jack Dongarra	Professor U of Tennessee netlib.org/utk/people/JackDongarra		numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology and tools for parallel computers, LINPACK, MPI, PVM, ScaLAPACK dblp
José Duato	Professor Technical U of Valencia, Spain gap.upv.es/people/jduato/english.html		multicomputer systems, interconnection networks, parallel algorithms, simulation dblp
Pradeep Dubey	Intel Research intel.com/research/people/bios/dubey_p.htm		Altivec, 80386/80486/Pentium, computer architecture, multithreading, multimedia processing dblp
Michel Dubois	Professor U of Southern California, EE usc.edu/dept/ceng/dubois/dubois.html		multiprocessor architecture/performance/algorithms, rapid prototyping engine for multiprocessors (RPM) dblp
Evelyn Duesterwald	IBM		interprocedural data flow analyses dblp
Carole Dulong	co-manager, IA-64 compiler group Intel		MMX, IA-64 compilation dblp
Nikil Dutt	Professor UC Irvine cecs.uci.edu/~dutt		embedded systems design automation dblp
Shantanu Dutt	Professor U of Illinois at Chicago, ECE ece.uic.edu/~dutt		parallel and distributed computing, place and route, fault-tolerant circuits, multicomputer architecture dblp
Robert W. Dutton	Professor Stanford U, EE www-tcad.stanford.edu/tcad/bios/dutton.html		MEMS, CAD Tools, Parascope, Pisces, Suprem dblp
Vaclav Dvorak	Professor Brno U of Technology, Czech Republic fee.vutbr.cz/~dvorak		computer architecture, parallel and distributed computing, embedded and configurable systems dblp
Sandhya Dwarkadas	Professor U of Rochester, CS cs.rochester.edu/u/sandhya		InterWeave, CASHMERE, ARCH: Architecture, Runtime, and Compiler integration for HPC, processing for low-power, InterAct dblp
Harry Dwyer	Bell Labs, Lucent cm.bell-labs.com/who/dwyer		out-of-order processors dblp
Matthew B. Dwyer	Professor Kansas State U cis.ksu.edu/~dwyer		software verification, Bandera, model checking, specification dblp
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Kemal Ebcioglu	IBM T. J. Watson		VLIW, dynamic compilation dblp
Carl Ebeling	Professor U of Washington, Seattle, CS cs.washington.edu/homes/ebeling		RaPiD, reconfigurable hardware dblp
Hans Eberle	senior staff engineer Sun Research research.sun.com/people/eberle		interconnetion networks, clusters dblp
Stephen A. Edwards	Professor Columbia U, CS cs.columbia.edu/~sedwards		embedded system design, domain-specific languages, compilers dblp
Lieven Eeckhout	postdoc Ghent U, Belgium elis.rug.ac.be/~leeckhou/		computer architecture, performance analysis, statistical modeling, analytical modeling, early design stage modeling dblp
Gregory K. Egan	Professor Monash U, Australia ecse.monash.edu.au/staff/egan		design / programming / applications of high-performance parallel computer architectures dblp
Susan J. Eggers	Professor U of Washington Seattle, CS cs.washington.edu/homes/eggers		DyC dynamic compilation, SMT simultaneous multithreading, SPIN dblp
Thorsten von Eicken	Professor (visiting) UC Santa Barbara, CS cs.ucsb.edu/~tve		Active Messages, Split-C, U-Net dblp
Rudolf Eigenmann	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~eigenman		parallel computing, optimizing compilers, software engineering, characterization of applications, performance evaluation and benchmarking dblp
Christine Eisenbeis	INRIA, Rocquencourt, France www-rocq.inria.fr/~eisenbei		register allocation, software pipelining dblp
Magnus Ekman	Sun microsystems ce.chalmers.se/~mekman		energy-efficient architecture, statistical techniques for architectural simulation, large memories dblp
Ahmed A. El-Amawy	Professor Louisiana State U ece.lsu.edu/amawy/amawy.html		parallel processing, computer architecture, clock distribution, fault tolerant computing, interconnection networks dblp
Tarek El-Ghazawi	Professor George Washington U seas.gwu.edu/~tarek		high-performance computing, parallel computer architectures, high-performance I/O, reconfigurable computing, experimental performance evaluations, computer vision, remote sensing dblp
Petru Eles	Professor Linkoping U, Linkoping, Sweden ida.liu.se/~petel		electronic design automation, hardware/software co-design, real-time systems, design of embedded systems, design for testability dblp
Joel Emer	Director Intel Microarchitecture Research intel.com/pressroom/kits/bios/jemer.htm		microarchitecture, Alpha microprocessors, quantitative analysis, performance modeling, SMT, prediction dblp
E. Allen Emerson	Professor U of Texas, Austin, CS cs.utexas.edu/users/emerson		model checking dblp
Dawson R. Engler	Professor Stanford U stanford.edu/~engler		Exokernel, tickC, metacompilation dblp
Michael D. Ernst	Professor MIT sdg.lcs.mit.edu/~mernst		program analysis, compilers dblp
Rolf Ernst	Professor Technical U of Braunschweig ida.ing.tu-bs.de/people/ernst/home.e.shtml		computer architecture, digital circuits, computer engineering dblp
M. Anton Ertl	Professor Technische U Wien, Austria complang.tuwien.ac.at/anton/home.html		compiler back-ends, Forth, interpreters, constraint logic programming, Linux and operating systems dblp
Roger Espasa	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/roger		vector architectures dblp
Daniel Etiemble	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~de		performance evaluation of clusters of multiprocessors and PCs, multivalued logic circuits dblp
William S. Evans	Professor U of British Columbia, Canada cs.ubc.ca/~will		information theory, data compression, computational geometry dblp
Guy Even	Professor Tel Aviv U, Israel eng.tau.ac.il/~guy		approximation algorithms for NP Complete problems related to VLSI, computer arithmetic, design of floating point units, systolic arrays dblp
Marius Evers	AMD		branch prediction dblp
Paraskevas Evripidou	Professor U of Cyprus cs.ucy.ac.cy/~skevos		parallel programming and debugging, pararallelizing compilers dblp
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Manuel A. Fähndrich	Microsoft Research research.microsoft.com/~maf		static program analysis, type systems, novel programming languages, Fugue, Vault, BANE dblp
Michael Faiman	(deceased) U of Illinois at Urbana-Champaign, CS cs.uiuc.edu/people/faculty/faiman.html		computer architecture, computer networks, ILLIAC I & II, graphical processing, device theory, circuit design dblp
Babak Falsafi	Professor Carnegie Mellon U, ECE ece.cmu.edu/~babak		microarchitecture, multiprocessors, memory coherence dblp
Jesse Z. Fang	Director Intel MRL Programming Systems Lab intel.com/research/people/bios/fang_j.htm		compiler/architecture research for ILP and threads, dynamic optimization for C/C++, object oriented languages, virtual machines and just-in-time compilation dblp
Paolo Faraboschi	Hewlett-Packard Labs, Cambridge		embedded computers, custom-fit processors dblp
Keith I. Farkas	Hewlett Packard WRL research.compaq.com/wrl/people/farkas/bio.html		low power, processor architecture, memory system performance dblp
Matthew K. Farrens	Professor UC Davis, CS huron.cs.ucdavis.edu/~farrens		architecture and design of high-performance single-chip processors dblp
Stuart Feldman	Director IBM Institute for Advanced Commerce research.ibm.com/iac/advisory-feldman.html		software engineering, programming languages, scientific computing, make dblp
Edward W. Felten	Professor Princeton U, CS cs.princeton.edu/~felten		secure internet programming, SHRIMP multicomputer dblp
Jeanne Ferrante	Professor UC San Diego www-cse.ucsd.edu/users/ferrante		SSA, predicated execution, compiler optimizations dblp
John Field	Research staff IBM Research research.ibm.com/people/j/jfield		program understanding and analysis tools, algorithms for program analysis, logics of programs, term- and graph-rewriting, program slicing, compiler optimization, incremental algorithms dblp
Tony Field	Senior Lecturer and Teaching Fellow Imperial College, UK doc.ic.ac.uk/~ajf		performance modelling of computer software and hardware, software performance optimisation, particle-based simulation of microbiological systems, discrete-event simulation, functional programming languages, compilers and run-time systems dblp
Robert Bruce Findler	Professor U of Chicago cs.uchicago.edu/people/robby		programming languages, DrScheme, software contracts dblp
Ulrich Finger	Director Institut Eurecom, France eurecom.fr/Resources/Direction/finger.html		parallel processing, parallel computer architecture dblp
Alan M. Finn	United Technologies Research Center users.erols.com/alanfinn		computer architecture with emphasis on embedded systems dblp
Charles N. Fischer	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~fischer/fischer.html		compilers, register allocation dblp
Joseph A. Fisher	Hewlett-Packard Labs, Cambridge hpl.hp.com/about/bios/josh_fisher.html Eckert-Mauchly (2003) award		ILP, branch prediction, VLIW, trace scheduling dblp
Kathleen Fisher	AT&T Research research.att.com/info/kfisher		domain-specific programming languages, Moby, PADS, Hancock dblp
Cormac Flanagan	Professor UC Santa Cruz CS soe.ucsc.edu/~cormac		software engineering, validation, defect detection dblp
Matthew Flatt	Professor U of Utah CS cs.utah.edu/~mflatt		programming languages, DrScheme, object-oriented programming, high-level operating systems dblp
Michael J. Flynn	Professor (emeritus) Stanford U umunhum.stanford.edu/~flynn Eckert-Mauchly (1992) award		computer architecture dblp
José A. B. Fortes	Professor U of Florida acis.ufl.edu/fortes		parallel processing, computer architecture, network-computing, fault-tolerant computing dblp
Jeff P. Foster	Professor U of Maryland, CS cs.umd.edu/~jfoster		tools and techniques to improve software quality, cqual dblp
Matthew Frank	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?mif		parallelization of programs with statically unpredictable dependencies, RAW dblp
Michael P. Frank	Professor U of Florida ECE cise.ufl.edu/~mpf		low-power computing, reversible computing, adiabatic circuits, reversible languages dblp
Manoj Franklin	Professor U of Maryland ece.umd.edu/~manoj		computer architecture especially ILP, compiling for ILP machines, memory systems dblp
Mark A. Franklin	Professor Washington U in St. Louis ccrc.wustl.edu/~jbf		computer architecture, parallel processing, systems performance evaluation, VLSI design dblp
Michael Franz	Professor UC Irvine ics.uci.edu/~franz		security and efficiency of mobile code, code compression, dynamic compilation, compiling for low-power dblp
Paul Franzon	Professor North Carolina State U, ECE ece.ncsu.edu/erl/faculty/paulf.html		high speed packaging and interconnect, high speed and low power chip design, micro electro mechanical machines, wafer-scale integration, IC yield modeling, VLSI chip design, communications systems design, molecular computers dblp
Christopher W. Fraser	Microsoft Research research.microsoft.com/~cwfraser/		code compression, code generation, editors dblp
Eby G. Friedman	Professor U of Rochester, EE ee.rochester.edu/users/friedman		VLSI circuits and systems, CMOS circuits, synchronization, clock distribution, pipelining, speed/power/area tradeoffs dblp
Jason Fritts	Professor Washington U in St. Louis ccrc.wustl.edu/~jefritts		media processors, embedded systems, ubiquitous computing, computer architecture, parallel processing, video and image processing dblp
W. Kent Fuchs	Professor Cornell U, ECE composer.ecn.purdue.edu/~fuchs (old)		dependable computer systems, testing and fault diagnosis of VLSI IC dblp
Donald S. Fussell	Professor U of Texas, Austin, CS cs.utexas.edu/users/fussell		computer architecture, computer graphics, database systems, design automation, fault-tolerant computing dblp
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Richard P. Gabriel	Sun Labs dreamsongs.com/Bio.html Allen Newell ((2004)) award		Lisp, CLOS dblp
Daniel D. Gajski	Professor UC Irvine cecs.uci.edu/~gajski		requirement/specification/design of embedded systems dblp
Abbas El Gamal	Professor Stanford U, ECE www-isl.stanford.edu/~abbas		information theory, communication complexity, VLSI design and CAD, programmable digital cameras dblp
Gregory R. Ganger	Professor Carnegie Mellon U, ECE ece.cmu.edu/~ganger		BSD FFS, exokernel, MEMS storage, DiskSim dblp
Jack Gannsle	editor Embedded Systems Programming ganssle.com		embedded systems
Guang R. Gao	Professor U of Delaware capsl.udel.edu/~ggao		computer architecture and systems, parallel and distributed systems, computational biology and bioinformatics, optimizing and parallelizing compilers, parallel programming, VLSI and application-specific system design dblp
Jean-Luc Gaudiot	Professor UC Irvine, EECS ece.uci.edu/faculty/gaudiot		parallel processing, functional languages, processor architecture, fault-tolerand computing dblp
Alan D. George	Professor U of Florida hcs.ufl.edu/~george		high-performance computer networks, parallel and distributed computing, high-performance computer architecture, fault-tolerant computing dblp
Manuel G. Gericota	Professor Polytechnic Instutute of Porto, ECE, Portugal dee.isep.ipp.pt/~mgg/indexe.html		design and test of digital systems, FPGA design and test, test methodologies for reconfigurable hardware systems, dynamic allocation of hardware resources in dynamically reconfigurable systems, reconfigurable systems management dblp
Rob Gerth	staff engineer Strategic CAD Labs, Intel		multi-processor verification dblp
Kourosh Gharachorloo	Google geocities.com/kourosh_info Maurice Wilkes (2004) award		high-end servers, Shasta, DASH, parallel computer architecture and software, commercial database and webserver performance dblp
Giorgio Ghelli	Professor U of Pisa, Italy di.unipi.it/~ghelli/ghelli.html		spatial logics, database programming languages, type theory dblp
Kanad Ghose	Professor Binghamton State U of New York, CS cs.binghamton.edu/~ghose		computer architecture, parallel and distributed processing, high-performance networking, VLSI systems, large-scale volume visualization dblp
Garth A. Gibson	Professor Carnegie Mellon U, CS cs.cmu.edu/~garth		RAID, storage, NASD dblp
Yossi Gil	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~yogi		software engineering, object-oriented pardigm, programming languages, parsing dblp
Roberto Giorgi	Professor U di Siena, Italy lucy.dii.unisi.it/~giorgi		coherence protocols for multiprocessors, behavior of user and system code, architectural simulation, multithreaded processors dblp
Tony Givargis	Professor UC Irvine cecs.uci.edu/~givargis		embedded system design and optimization dblp
Andy Glew	Intel Microprocessor Research Labs intel.com/research/mrl/people/glew_a.htm		microarchitecture, P6, MMX dblp
Neal Glew	Intel Research intel.com/research/people/bios/glew_n.htm		typed assembly language dblp
Maya Gokhale	Sarnoff Corp		reconfigurable hardware, C to HDL dblp
Seth Copen Goldstein	Professor Carnegie Mellon U, CS cs.cmu.edu/~seth		reconfigurable hardware, PipeRench, nanotechnology, lazy threads dblp
German S. Goldszmidt	IBM T. J. Watson cs.columbia.edu/~german (old)		distributed debugging, programming languages for distributed systems, e-commerce, distributed systems dblp
Ronaldo A. L. Gonçalves	Professor U Estadual de Maringa, Brazil din.uem.br/~ronaldo		parallel and high performance computing, parallel / superscalar / multithreaded architectures, performance evaluation of computer architecture, operating systems and compilers dblp
Georges Gonthier	Microsoft Research Cambridge research.microsoft.com/~gonthier		four-color theorem, programming languages, program verification, lambda calculus dblp
Antonio Gonzalez	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/antonio		superscalar processors dblp
José González	Professor U de Murcia, Spain ditec.um.es/~joseg		value prediction, CC-NUMA, microarchitecture dblp
James R. Goodman	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~goodman		high-performance computer architecture, memory systems, shared-memory multiprocessing dblp
David W. Goodwin	principal engineer Hewlett-Packard VSSAD group (old)		binary optimizations, Alpha performance analysis, Spike, executable interprocedural dataflow analysis dblp
Gerhard Goos	Professor U Karlsruhe, Germany i44w3.info.uni-karlsruhe.de/~ggoos		object-oriented programming, software components, compiler correctness, VERIFIX dblp
Ganesh Gopalakrishnan	Professor U of Utah, CS cs.utah.edu/~ganesh		Utah Verifier (UV), formal verification, asynchronous circuits and systems dblp
Michael J. C. Gordon	Professor Cambridge U, UK cl.cam.ac.uk/users/mjcg		HOL, formal verification dblp
James Gosling	Sun Labs java.sun.com/people/jag		Java, Emacs, NeWS window system dblp
Allan Gottlieb	Professor New York U, CS cs.nyu.edu/cs/faculty/gottlieb		Ultracomputer, parallel computers dblp
Ramaswamy Govindarajan	Professor Indian Institute of Science, Bangalore, India serc.iisc.ernet.in/~govind		ILP compilation, compilation techniques for architectural features, compilation for embedded/DSP processors, distributed shared memory, high performance architectures, programming models for DSP dblp
Susan L. Graham	Professor UC Berkeley, CS cs.berkeley.edu/~graham		parsing, compiler construction, gprof dblp
F. Gail Gray	Professor Virginia Tech, EE ecpe.vt.edu/faculty/gray.html		VHDL, high level modeling and design, high level test generation, fault tolerant systems, reconfigurable arrays, coding theory dblp
Jim Gray	Microsoft Research research.microsoft.com/~gray Turing (1998) award		transactions, databases, scalable servers dblp
Ronald I. Greenberg	Professor Loyola U, Chicago math.luc.edu/~rig		algorithms, parallel computation, computer architecture, VLSI, discrete mathematics dblp
Mark R. Greenstreet	Professor U of British Columbia CS, CA cs.ubc.ca/~mrg		VLSI design and verification, hybrid systems, dynamical systems, formal methods, asynchronous logic dblp
David Gregg	Professor Trinity College, Dublin, Ireland cs.tcd.ie/David.Gregg		interpreters, hardware compilation, compiling for instruction level parallelism, software pipelining, register allocation, branch prediction dblp
Ed Grochowski	Intel MRL intel.com/research/people/bios/grochowski_e.htm		Intel 486/Pentium/Pentium II/Itanium dblp
Thomas R. Gross	Professor ETH Zurich, Switzerland lst.inf.ethz.ch/people/trg.html		MIPS, Warp, iWarp, Fx dblp
Dan Grossman	Professor U of Washington, Seattle, CS cs.washington.edu/homes/djg		Cyclone, type theory dblp
Andrew Grove	Chairman of the Board Intel developer.intel.com/pressroom/kits/bios/grove.htm		semiconductors, Intel
Orna Grumberg	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/users/orna		computer-aided verification of software and hardware, modularity, abstraction, refinement and counterexamples, symmetry, temporal logics, equivalences and preorders, distributed model checking, static analysis and model checking, coverage and vacuity, sat-based model checking, games for model checking, automata on infinite objects dblp
Dirk Grunwald	Professor U of Colorado, CS cs.colorado.edu/~grunwald		computer systems dblp
Michael K. Gschwind	Researcher IBM TJ Watson Research Center research.ibm.com/people/m/mikeg		dynamic compilation, binary translation, dynamic optimization, BOA, DAISY, system architecture, microarchitecture (RS6000 and S/390), compilation, power-modelling and power-aware architecture, application-specific processors, SOC dblp
P. Glenn Gulak	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~gulak		VLSI in digital communications and signal processing, computer architecture, VLSI design and applications dblp
Carl A. Gunter	Professor U of Illinois at Urbana-Champaign CS www-faculty.cs.uiuc.edu/~cgunter/		security, networks, programming languages, software engineering dblp
Anoop Gupta	Senior Researcher Microsoft Research research.microsoft.com/~anoop		DASH, FLASH, multimedia dblp
Rajesh Gupta	Professor UC Irvine ics.uci.edu/~rgupta		algorithms for VLSI design automation, CAD for embedded and portable systems, computer architecture dblp
Rajiv Gupta	Professor U of Arizona, CS cs.arizona.edu/people/gupta		path-sensitive optimizations, compiler back-end dblp
Sumit Gupta	Tallwood Venture Capital cecs.uci.edu/~sumitg		SPARK, high-level synthesis, reconfigurable computing dblp
John R. Gurd	Professor U of Manchester, UK cs.man.ac.uk/cnc/staff/john/home.html		Manchester data-flow computer, parallel computer systems dblp
Samuel Z. Guyer	postdoc U of Texas Austin CS cs.utexas.edu/users/sammy		high-level optimizations, domain-specific optimizations, pointer analysis, automatic error checking, compiler-assisted memory management dblp
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Haldun Hadimioglu	Professor Polytechnic U, NY cis.poly.edu/haldun		high-speed optical switch design, novel processor design, memory hierarchy issues and I/O dblp
Erik Hagersten	Professor Uppsala U, Sweden docs.uu.se/~eh		shared-memory multiprocessor architectures, cache-only memory architectures (COMA), dynamic caching algorithms, access pattern categorization, dynamically adapting architectures dblp
Ibrahim N. Hajj	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?i-hajj		CAD, VLSI circuits and systems dblp
Mary W. Hall	Professor U of Southern California isi.edu/~mhall		DIVA: Data-IntensiVe Architecture, DEFACTO: Design Environment for Adaptive Computing TechnOlogy, combining compile-time and run-time parallelization dblp
Richard W. Hamming	(deceased) Bell Labs, Lucent/Naval Postgraduate School cm.bell-labs.com/cm/cs/alumni/hamming Turing (1968) award		error correcting codes, programming languages, numerical analysis, digital filters dblp
Richard E. Hank	Hewlett-Packard crhc.uiuc.edu/IMPACT/people/graduated/Rick_Hank.html (old)		region-based compilation, VLIW and EPIC compilation dblp
Chris Hankin	Professor Imperial College, UK doc.ic.ac.uk/chris.html		program analysis, safety critical systems, coordination languages dblp
Robert Harper	Professor Carnegie Mellon U, CS www-2.cs.cmu.edu/~rwh		programming languages design/semantics/verification/implementation, types in compilation, logical frameworks and meta-languages, scientific computing, trustless grid computing dblp
Tim Harris	Researcher Microsoft Research Cambridge, UK research.microsoft.com/~tharris		programming languages, managed runtime environments, multi-threaded software, transactional programming dblp
Reiner Hartenstein	Professor U Kaiserslautern, Germany hartenstein.de		reconfigurable computing/supercomputing/computer architectures/SoC, FPGAs, software/configware co-compilation, hardware description languages, microprogramming dblp
Soha Hassoun	Professor Tufts U eecs.tufts.edu/~soha		architectural and sequential optimizations, timing analysis, regularity extraction, configurable computing dblp
Scott Hauck	Professor U of Washington Seattle, EE ee.washington.edu/faculty/hauck		reconfigurable hardware, Chimaera dblp
John P. Hayes	Professor U of Michigan eecs.umich.edu/~jhayes		quantum computers, massively parallel embedded systems, computer architectures for safety-critical applications, verification and testing of systems-on-a-chip, automated synthesis and layout dblp
Lei He	Professor U of Wisconsin-Madison engr.wisc.edu/ece/faculty/he_lei.html		CAD for VLSI, power-efficient circuits and computer systems, numerical and combinatorial optimization dblp
Xubin He	Professor Tennessee Tech U, ECE ece.tntech.edu/hexb		storage cache and disk I/O, networked storage, VHDL, performance evaluation dblp
Görel Hedin	Professor Lund Institute of Technology, Sweden cs.lth.se/home/Gorel_Hedin/		object-oriented languages and design, domain-specific languages, language implementation techniques, interactive software development environments dblp
Jan Heering	Professor Centrum voor Wiskunde en Informatica, Netherlands homepages.cwi.nl/~jan		compilers, program restructuring, software engineering dblp
Eric C. R. Hehner	Professor U of Toronto, CS, Canada cs.toronto.edu/~hehner		formal methods of program design, programming language semantics, compiler design, high-level circuit design dblp
John Heinlein	Transmeta www-flash.stanford.edu/~heinlein		FLASH dblp
Mark Heinrich	Professor University of Central Florida, CS csl.cs.ucf.edu/~heinrich		active memory and I/O subsystems, novel computer architectures, parallel computer architecture, data-intensive computing, scalable cache coherence protocols, multiprocessor design and simulation methodology, hardware/software co-design dblp
Nevin Heintze	Agere Systems cm.bell-labs.com/cm/cs/who/nch		set-based analysis, pointer analysis, verification dblp
Laurie J. Hendren	Professor McGill U, Montreal, Canada sable.mcgill.ca/~hendren		compilers, pointer analyses, McCAT, Soot dblp
John L. Hennessy	Professor Stanford U www-flash.stanford.edu/~jlh von Neumann Medal (2000), Eckert-Mauchly (2001) award		FLASH, MIPS dblp
Dana S. Henry	Professor Yale U, CS thor.cs.yale.edu/~dana		Ultrascalar, NIC, FLIP dblp
Thomas A. Henzinger	Professor U of California at Berkeley, ECE www-cad.eecs.berkeley.edu/~tah		system design/modeling/implementation/verification, formal verification, embedded systems dblp
Martin C. Herbordt	Professor Boston U ? people.bu.edu/herbordt		architecture and evaluation of massively parallel computers, network caching dblp
Maurice Herlihy	Professor Brown U CS cs.brown.edu/people/mph/home.html		distributed computing, transactional memory, lock-free programming dblp
Paul N. Hilfinger	Professor UC Berkeley, CS cs.berkeley.edu/~hilfingr		Lisp, Titanium (Java), PRCS dblp
Mark D. Hill	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~markhill		multiprocessors, system architecture, DSM, cache memory dblp
Sébastien Hily	senior researcher Intel Microprocessor Research Labs irisa.fr/caps/people/hily/index_en.htm (old)		microprocessors, computer architecture, simultaneous multithreading dblp
Michael Hind	Researcher IBM T. J. Watson research.ibm.com/people/h/hind/		Jikes, interprocedural analysis, automatic parallelization, dynamic optimization dblp
Glenn J. Hinton	director of IA-32 Microarchitecture Development Intel intel.com/pressroom/kits/bios/hinton.htm Maurice Wilkes (2002) award		i960, Pentium Pro, Pentium II, Pentium 4
Ralf Hinze	Professor U Bonn, Germany /www.informatik.uni-bonn.de/~ralf		functional programming, Haskel dblp
C. Antony R. Hoare	Microsoft Research, Cambridge, UK research.microsoft.com/~thoare Turing (1980) award		programming methods and languages, proof techniques for programs, distributed computing, hardware compilation,P dblp
James C. Hoe	Professor Carnegie Mellon U, ECE ece.cmu.edu/~jhoe		operation-centric hardware synthesis, term-rewriting systems, network interfaces for clusters dblp
Martin Hofmann	Professor Ludwig-Maximilians U Muenchen tcs.informatik.uni-muenchen.de/~mhofmann		type theory, principles of programming languages, semantics, category theory, mathematical logic, formal methods dblp
H. Peter Hofstee	IBM Austin Research Lab		parallel algorithms, microarchitecture, timing analysis, asynchronous circuits, logic design dblp
Urs Hölzle	Professor UC Santa Barbara, CS cs.ucsb.edu/~urs		object-oriented programming languages, software engineering, OSUIF, StrongTalk, HotSpot JVM, indirect branch prediction dblp
Gerard J. Holzmann	Bell Labs cm.bell-labs.com/cm/cs/who/gerard		SPIN, model checking dblp
Sangjin Hong	Professor State U of New York at Stony Brook ECE ece.sunysb.edu/~snjhong/		low power VLSI, digital signal processing, embedded designs dblp
Mark Horowitz	Professor Stanford U www-flash.stanford.edu/~horowitz		FLASH, CAD tools, low power design dblp
R. Nigel Horspool	Professor U of Victoria, Canada cs.uvic.ca/~nigelh		compilers, programming language (Java) implementations, document conversion, data compression, XML, HTML, string search dblp
Susan B. Horwitz	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~horwitz/horwitz.html		language-based programming environments, program slicing differencing and merging, static analysis, interprocedural dataflow analysis dblp
Antony L. Hosking	Professor Purdue U, CS cs.purdue.edu/homes/hosking		programming language design and implementation, database and persistent programming languages, object-oriented database systems, dynamic memory management, compiler optimization, architectural support for programming languages and applications dblp
Michael S. Hsiao	Professor Virginia Tech, ECE visc.vt.edu/~mhsiao		test and verification, CAD, low-power architecture dblp
Wilson C. Hsieh	Professor U of Utah, CS cs.utah.edu/~wilson		compilers, programming languages, systems, architecture dblp
Wei-Chung Hsu	Professor U of Minesotta, CS www-users.cs.umn.edu/~hsu		high performance processor and system architectures, compiler optimizations, runtime optimization systems dblp
Y. Charlie Hu	Professor Purdue U, ECE ece.purdue.edu/~ychu		distributed systems, operating systems, networking, high performance computing dblp
Yiming Hu	Professor U of Cincinnati ececs.uc.edu/~yhu		memory architecture, high performance I/O systems, file systems, virtual memory, high performance Web servers, embedded systems, parallel and distributed computing dblp
Michael C. Huang	Professor U of Rochester, ECE ece.rochester.edu/~mihuang		computer architecture, processor microarchitecture, energy-efficient system and processor architecture, processing-in-memory dblp
Ali R. Hurson	Professor Penn State U cse.psu.edu/~hurson		conventional and unconventional concurrent and parallel systems, object oriented databases, multi-databases, hybrid dataflow architecture, global information processing in mobile and wireless environments dblp
Brad L. Hutchings	Professor Brigham Young U, EE ee.byu.edu/faculty/hutch		application-specific processors, run-time reconfiguration, automatic target recognition dblp
Kai Hwang	Professor U of Southern California ceng.usc.edu/~kaihwang		computer architecture, digital arithmetic, parallel processing, distributed computing dblp
Wen-mei W. Hwu	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/Faculty/hwu.html Maurice Wilkes (1998) award		IMPACT, Trimaran, computer architecture, compilers dblp
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Paolo Ienne	Professor Ecole Polytechnique Federale de Lausanne, Switzerland lapwww.epfl.ch/people/ienne		computer and processor architecture, language-based VLSI design flows, computer arithmetic, systolic array processors, hardware for neural networks, design for testability dblp
Roberto Ierusalimschy	Professor PUC-Rio, Brazil inf.puc-rio.br/~roberto		domain-specific languages dblp
Liviu Iftode	Professor U of Maryland, CS cs.umd.edu/~iftode		operating systems, distributed systems, networking, embedded and pervasive computing, distributed shared memory dblp
Masaharu Imai	Professor Osaka U, Japan vlsilab.ics.es.osaka-u.ac.jp/~imai		application-specific processors dblp
Mary Jane Irwin	Professor Penn State U cse.psu.edu/~mji		computer architecture, computer arithmetic, VLSI systems design, low power design, electronic design automation dblp
Randall D. Isaac	Vice President of Systems, Technology, and Science IBM Research		semiconductor technology dblp
Ravishankar K. Iyer	Professor U of Illinois at Urbana-Champaign, ECE crhc.uiuc.edu/Faculty/iyer.html		scientific/commercial workload characterization, interconnection networks, memory systems, latency hiding techniques, performance evaluation dblp
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Bruce Jacob	Professor U of Maryland, EE ee.umd.edu/~blj		computer architecture and microarchitecture, memory hierarchies, embedded systems, Verilog modeling, low-level operating systems design, computer music dblp
T. Matthew Jacob	Professor Indian Institute of Science, Bangalore, India csa.iisc.ernet.in/people/faculty/data/mjt.htm		performance aspects of computer architecture, operating systems, parallel processing
Quinn Jacobson	Sun		trace processors dblp
Margarida F. Jacome	Professor U of Texas, Austin, ECE horizon.ece.utexas.edu/~jacome		embedded VLIW/EPIC processors, retargetable compilers, system-level design, hardware/software codesign, high-level synthesis dblp
Joxan Jaffar	Professor National University Singapore comp.nus.edu.sg/~joxan		programming languages and applications, logic and constraint programming, program analysis and verification dblp
Suresh Jagannathan	Professor Purdue U, CS cs.purdue.edu/homes/suresh		program analysis and compiler design, peer-to-peer computing, distributed storage architectures dblp
Axel Jantsch	Professor Royal Institute of Technology, Stockholm, Sweden ele.kth.se/~axel		MASCOT, VLSI design and synthesis, system level specification/modelling/validation dblp
Alan Jeffrey	Professor DePaul U, Chicago, IL fpl.cs.depaul.edu/ajeffrey		foundations of programming languages and computer security, semantics of higher order languages, mathematical models of object-based systems, type systems, concurrent and distributed languages dblp
Stephen Jenks	Professor UC Irvine, ECE ece.uci.edu/~sjenks		parallel computing, large-scale distributed memory systems, thread migration, real-time distributed systems dblp
Tor E. Jeremiassen	Texas Instruments cm.bell-labs.com/cm/cs/who/tor (old)		computer architecture, DSPs, compilers dblp
Ahmed Amine Jerraya	TIMA Laboratory, IMAG, Grenoble, France tima-cmp.imag.fr/Homepages/jerraya/jerraya.html		hardware-software co-design dblp
Chris Jesshope	Professor U of Amsterdam CS, Netherlands carol.science.uva.nl/~jesshope/		microarchitecture, e-learning
Somesh Jha	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~jha		software engineering, model checking, security dblp
Daniel A. Jiménez	Professor Rutgers U CS cs.utexas.edu/users/djimenez (old)		microarchitecture, branch prediction, compilers and microarchitectures dblp
Hai Jin	Professor Huazhong U, China hust.edu.cn/hjin		computer architecture and cluster computing, parallel and distributed computing, high performance network storage systems and Parallel I/O, web and network security, fault tolerance, performance evaluation and benchmarking dblp
Lizy Kurian John	Professor U of Texas, Austin, ECE ece.utexas.edu/~ljohn		processor architecture, workload characterization, native signal processing, compilers for innovative architectures dblp
Eric E. Johnson	Professor New Mexico State U atanasoff.nmsu.edu/ejohnson/ejohnson.html		architectures for parallel and distributed computing, computer performance evaluation, simulation, mobile computing/wireless networks, hf radio networks, cryptography, network security dblp
Richard Johnson	Hewlett-Packard (old) trimaran.org/car_group/richard_johnson.html (old)		predication, dataflow-analysis, compilers dblp
Ross Johnson	IBM cs.wisc.edu/~galileo/ross/ross.html		AS/400, shared memory multiprocessors
Teresa L. Johnson	Hewlett-Packard Corporation crhc.uiuc.edu/IMPACT/people/graduated/Teresa_Johnson.html (old)		cache performance, cache management dblp
Alex K. Jones	Professor U of Pittsburgh, ECE engr.pitt.edu/electrical/people/jones_alex.html		high-level synthesis dblp
Mark T. Jones	Professor Virginia Tech, EE ecpe.vt.edu/faculty/mtjones.html		high-performance computation, parallel and configurable computing, networks of embedded systems, distributed wireless sensor networks, distributed decision support systems, computational fabrics, numerical simulation, parallel algorithms dblp
Neil D. Jones	Professor DIKU, U of Copenhagen, Denmark diku.dk/users/neil		programming languages, compilers, theory of computation dblp
Simon L. Peyton Jones	Microsoft Research research.microsoft.com/~simonpj		the Haskell Glasgow compiler, functional programming languages dblp
Norman P. Jouppi	Hewlett-Packard WRL wwww.hpl.hp.com/about/bios/norman_jouppi.html		telepresence, graphics, CACTI, memory systems dblp
Roy D. C. Ju	Intel MRL intel.com/research/mrl/people/ju_roy.htm		compiler optimization, program analysis, computer architecture, and parallel processing dblp
Ben H. H. Juurlink	Professor Delft U, Netherlands ce.et.tudelft.nl/~benj		application-specific ISA extensions, multiple-issue processors, low-power techniques, hierarchical memory systems, parallel algorithms/architectures/programming/cost models dblp
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M. Frans Kaashoek	Professor MIT pdos.lcs.mit.edu/~kaashoek		Click modular router, Exokernel, tick-C, Amoeba/Orca dblp
Péter Kacsuk	head of the Parallel and Distributed Systems Laboratory Computer and Automation Research Institute of the Hungarian Academy of Sciences ultra10.lpds.sztaki.hu/staff/kacsuk_peter/sajat_honlap		paralel logic programming, parallel computer architectures, parallel software engineering, Grid tools dblp
David R. Kaeli	Professor Northeastern U, ECE ece.neu.edu/faculty/kaeli.html		branch prediction, I/O workload characterization, memory hierachy design, object-oriented code performance, 3-D VLSI design, compiler back-ends, trace-driven simulation dblp
Alain Kägi	Researcher Intel Microprocessor Research Labs intel.com/research/mrl/people/kagi_a.htm		memory bandwith, optimized synchronization dblp
Krishnan Kailas	research staff IBM T. J. Watson e-kailas.net		low-power embedded architectures and DSP, microarchitecture and compilation for Clustered ILP processors dblp
Samuel N. Kamin	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~kamin		programming languages, software components, functional programming applied to scientific computation, denotational semantics, program specification and verification, domain-specific languages dblp
Mahmut Taylan Kandemir	Professor Penn State U cse.psu.edu/~kandemir		embedded systems, optimizing compilers, power-aware computing, multi-dimensional databases dblp
Russell Kao	senior staff engineer Sun Research research.sun.com/people/rkao		computer architecture, CAD, HP-PA, mixed switch-level/circuit level simulation dblp
Wolfgang Karl	Professor Muenchen Technical U, Germany wwwbode.cs.tum.edu/~karlw		computer architecture, microprocessors, computer and systems design, parallel and distributed systems, DSM, scalable coherent interface, fault tolerance, high availability, hot-swap, cache architectures, reconfigurable computing dblp
Hironori Kasahara	Professor Waseda U, Tokio, Japan kasahara.elec.waseda.ac.jp/kasahara.en.html		supercomputing, multiprocessor architectures, scheduling algorithms, parallelizing compilers, electronic circuit simulation dblp
Daniel Kästner	Senior Software Engineer AbsInt GmbH rw4.cs.uni-sb.de/~kaestner		embedded systems, retargetable compiler construction, code generation and optimization, generative programming, Java, integer linear programming, program analysis, scheduling, document processing dblp
Ryan Kastner	Professor UC Santa Barbara ECE ece.ucsb.edu/~kastner		embedded systems, reconfigurable computing, compilers, sensor networks dblp
Manolis G. H. Katevenis	Professor U of Crete, Grece archvlsi.ics.forth.gr/~kateveni		packet switch architecture, high-speed networks, computer architecture, VLSI dblp
Vinod Kathail	R&D Program Manager Hewlett-Packard trimaran.org/car_group/vinod_kathail.html (old)		Trimaran, PICO, EPIC, Elcor dblp
Srinivas Katkoori	Professor U of South Florida vcapp.csee.usf.edu/~katkoori		high level synthesis, low power synthesis, VLSI CAD for deep sub-micron regime, reconfigurable computing for space applications dblp
Joost-Pieter Katoen	Professor RWTH Aachen University, Germany www-i2.informatik.rwth-aachen.de/~katoen		semantics, probabilistic verification, software verification, process algebra, formal specification dblp
Randy H. Katz	Professor UC Berkeley, CS cs.berkeley.edu/~randy		network computing, communications-oriented service architectures dblp
Alireza Kaviani	Xilinx Research eecg.toronto.edu/~kaviani (old)		FPGA design dblp
Stefanos Kaxiras	Professor U of Patras, Greece cs.wisc.edu/~kaxiras		SMP, cache decay, Datascalar dblp
Tom Kean	Director Algotronix Ltd. algotronix.com/people/tom		Xilinx XC6200 FPGA architecture, reconfigurable computing dblp
Stephen W. Keckler	Professor U of Texas, Austin, CS cs.utexas.edu/users/skeckler		M-Machine, VLSI circuit design dblp
Gershon Kedem	Professor Duke U, CS kedem.cs.duke.edu		high performance memory systems dblp
Diana Keen	Professor Cal Poly csc.calpoly.edu/~dkeen		computer architecture, compilers, intelligent memory dblp
Robert M. Keller	Professor Harvey Mudd College cs.hmc.edu/~keller		programming languages: functional/parallel/real-time/logic, genetic programming dblp
Paul H. J. Kelly	Reader Imperial College of Science, Technology and Medicine, London, UK doc.ic.ac.uk/~phjk		computer systems issues underlying performance, performance evaluation / modelling / prediction, languages, compilers and operating systems for parallel computing dblp
Ken Kennedy	Professor Rice U, CS cs.rice.edu/~ken		vectorization, ParaScope, HPF, HPC dblp
Brian W. Kernighan	professor Princeton U, CS cs.princeton.edu/~bwk		C, programming, AWK, AMPL dblp
Christoph W. Keßler	Professor Linkoping U, Sweden ida.liu.se/~chrke/		parallel computing, compilers for instruction-level parallel and embedded processors, automatic parallelization dblp
Richard E. Kessler	Hewlett-Packard Research		processor caches, performance evaluation dblp
Kurt Keutzer	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~keutzer		MESCAL, embedded processor compilation, logic synthesis, test and timing verification, BACPAC dblp
Tom Kilburn	Professor (deceased) U of Manchester, UK computer50.org/mark1/kilburn.html Eckert-Mauchly (1981) award		Mark1, MUSE/Atlas, MU5 dblp
Earl Killian	Chief Architect Tensilica killian.com/earl		Pixie, processor architecture, MIPS, finger, SMTP dblp
Eun Jung Kim	Professor Texas A&M U, CS faculty.cs.tamu.edu/ejkim		computer architecture, power efficient systems, parallel/distributed systems, computer networks, cluster computing, QoS support in cluster networks and Internet, performance evaluation, fault-tolerant computing dblp
Shin-Dug Kim	Professor Yonsei U, Korea supercom.yonsei.ac.kr/~sdkim		advanced computer architectures, parallel processing systems, memory system design, heterogeneous Web computing, agent based Internet computing dblp
Taewhan Kim	Professor KAIST, Korea vlsisyn.kaist.ac.kr/~tkim		embedded system design, architecture-level synthesis for system-on-chip, logic-level synthesis, high-level synhesis, routing for FPGAs dblp
David Kinniment	Professor U of Newcastle upon Tyne EE, UK staff.ncl.ac.uk/david.kinniment/		synchronization, arbitration, metastability, asynchronous design, computer systems and microelectronics education dblp
Michael Kishinevsky	Strategic CAD Labs, Intel intel.com/research/people/bios/kishinevsky_m.htm		high-level and asynchronous design, reactive systems, theory of concurrency dblp
Artur Klauser	Intel, VSSAD cs.colorado.edu/~klauser (old)		ILP, computer architecture and microarchitecture, compiler optimizations, operating systems, distributed and parallel systems, high-performance computing, multipath execution dblp
Tom Knight	Professor MIT ai.mit.edu/people/tk/tk.html		microbial engineering, reversible and low energy computing, VLSI microdisplays, Abacus (SIMD), transit, transactional execution of programs dblp
Jens Knoop	Professor U of Viena, Austria complang.tuwien.ac.at/knoop		lazy code motion, programming languages and compilers, formal methods, program analysis/verification/optimisation/tools, Internet dblp
Donald E. Knuth	Professor (emeritus) Stanford U, CS www-cs-faculty.stanford.edu/~knuth Turing (1974) award, National Medal of Science (1979)		parsing, Algol 60, profiling, TeX, algorithms dblp
Seok-Bum Ko	Professor U of Saskatchewan EE, Canada engr.usask.ca/~sek867		FPGA, microprocessors dblp
Peter M. Kogge	Professor Notre Dame U nd.edu/~kogge		massively parallel processing architectures, advanced VLSI technology and architectures, parallel algorithms and applications, processing in memory dblp
Cheng-Kok Koh	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~chengkok/		layout-driven synthesis, interconnect-driven floorplanning and placement, global routing, clock synthesis, reduced-order modeling, power-supply network analysis and synthesis, very-high performance circuit design and synthesis dblp
Philip Koopman	Professor Carnegie Mellon U, ECE ece.cmu.edu/~koopman		Ballista, embedded Computing, stack machines, Forth dblp
David M. Koppelman	Professor Louisiana State U ece.lsu.edu/koppel		interconnection networks, multiprocessors dblp
Israel Koren	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/koren		VLSI yield, CAD for yield estimation and reliability, fault tolerance in real-time systems, computer arithmetic dblp
Nectarios G. Koziris	Professor National Technical U of Athens, Greece cslab.ece.ntua.gr/~nkoziris		parallel processing, parallel architectures, distributed systems, computer architecture dblp
Christoforos E. Kozyrakis	Professor Stanford U csl.stanford.edu/~christos		microprocessor architecture and design, IRAM dblp
Andreas Krall	Professor Technische U Wien, Austria complang.tuwien.ac.at/andi/home.html		object oriented languages, compiler back ends and computer architecture, logic programming, compilation for embedded processors dblp
Ulrich Kremer	Professor Rutgers U, CS athos.rutgers.edu/~uli		power and energy management, distributed embedded systems, compilation, data layout, performance prediction models dblp
Chandra Krintz	Professor UC Santa Barbara, CS cs.ucsb.edu/~ckrintz		adaptive compilation, mobile Java code dblp
Daniel Kroening	postdoc Carnegie Mellon U kroening.com		computer architecture, formal verification dblp
John D. Kubiatowicz	Professor UC Berkeley, CS cs.berkeley.edu/~kubitron		IRAM, Oceanstore, Alewife, quantum computers dblp
William J. Kubitz	Professor (emeritus) U of Illinois at Urbana-Champaign, CS cs.uiuc.edu/people/faculty/kubitz.html		VLSI physical design, computer graphics, converged media, mobile/wireless dblp
David J. Kuck	Chairman Kuck and Associates, Inc Eckert-Mauchly (1993) award, Charles Babbage award		parallel architectures, scientific computation, paralellizing compilers, Parafrase, KAP, KAI dblp
Philip J. Kuekes	Hewlett-Packard Labs hpl.hp.com/research/qsr/staff/kuekes.html		Teramac, systolic computation dblp
Sanjeev Kumar	Computer Architect Researcher Intel MRL intel.com/research/people/bios/kumar_s.htm		computer architecture, software systems dblp
H. T. Kung	Professor Harvard U eecs.harvard.edu/~htk		networking, systolic arrays, parallel computing dblp
Fadi J. Kurdahi	Professor UC Irvine eng.uci.edu/faculty/kurdahi/fadi.html		high-level synthesis, estimation and design methodology of large scale systems dblp
Jeffrey Kuskin	Atheros Communications www-flash.stanford.edu/~jsk (old)		Stanford FLASH multiprocessor dblp
Bradley C. Kuszmaul	Senior Research Scientist Supercomputing Technologies Group MIT bradley.csail.mit.edu/~bradley		CM-5, Ultrascalar, computer chess (StarTech and *Socrates), Cilk dblp
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Konrad Lai	Manager Intel Hillsboro Microarchitecture Labs intel.com/research/people/bios/lai_k.htm		microprocessor/memory/system architecture dblp
Monica S. Lam	Professor Stanford U suif.stanford.edu/~lam		SUIF, software pipelining, automatic parallelization, compilers dblp
Leslie Lamport	Microsoft Research lamport.org		Temporal Logic of Actions (TLA), Lamport clocks, Latex, parallel computation, metastability in asynchronous systems, formal methods, Byzantine agreement dblp
Butler W. Lampson	Microsoft Research research.microsoft.com/lampson		computer architecture, local area networks, raster printers, page description languages, operating systems, remote procedure call, programming languages and semantics, fault-tolerant computing, transaction processing, computer security, Alto personal distributed computing system, Xerox 9700 laser printer, two-phase commit protocol dblp
Anders Landin	Sun Microsystems sics.se/~landin (old)		multiprocessor architecture, memory systems, cache coherence, COMA, shared-memory application behaviour, architecture evaluation techniques, multiprocessor simulation dblp
Tomas Lang	Professor UC Irvine ece.uci.edu/faculty/lang.html		hardware for arithmetic dblp
Josep-Lluis Larriba-Pey	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/larri		software trace cache, branch prediction, performance of numerical algorithms dblp
James R. Larus	senior researcher Microsoft Research research.microsoft.com/~larus		program measurement, fine-grain shared memory, Wisconsin Wind Tunnel, SPIM, PP, QPT, EEL, path profiling dblp
Rudy Lauwereins	Professor U of Leuven, Belgium lesbos.esat.kuleuven.ac.be/dpt_people/person.php3?id=3		embedded systems design, architectures/methods/tools for smart networked devices dblp
Luciano Lavagno	Professor Politecnico di Torino/Cadence, Italy polimage.polito.it/~lavagno		asynchronous circuit design and testing, hardware/software co-design of embedded systems dblp
Daniel M. Lavery	Intel Corporation		compilation for Itanium dblp
Edward D. Lazowska	Professor U of Washington, Seattle, CS cs.washington.edu/people/faculty/lazowska		design/implementation/analysis of high-performance computing and communication systems dblp
Gary T. Leavens	Professor Iowa State U CS cs.iastate.edu/~leavens		multiple dispatch, multijava, formal methods (JML) dblp
Alvin R. Lebeck	Professor Duke U, CS cs.duke.edu/~alvy		computer systems, memory systems, energy-efficient computing, fast memory simulation, ICE, CURIOUS dblp
Ben Lee	Professor Oregon State U, ECE hubbard.ece.orst.edu/~benl		software and architectural support for multithreading dblp
Corinna G. Lee	ATI Technologies eecg.utoronto.ca/~corinna (old)		UTDSP benchmark suite, performance of 3D graphics chips dblp
Edward A. Lee	Professor UC Berkeley, ECE ptolemy.eecs.berkeley.edu/~eal		Ptolemy, DSP, embedded systems dblp
Gyungho Lee	Professor University of Illinois at Chicago, ECE ece.uic.edu/People/lee.htm		DICE: cache-only memory multiprocessor, access-region cache: scalable memory pipeline, Amanita: system hardening, cache for embedded applications dblp
Hsien-Hsin Sean Lee	Professor Georgia Tech, ECE ece.gatech.edu/~leehs		microarchitecture, compilers dblp
Jaejin Lee	Professor Michigan State U cse.msu.edu/~jlee/		compilers, programming languages, HPC, memory consistency, processor-in-memory dblp
John A. N. Lee	Professor Virginia Tech, CS ei.cs.vt.edu/~janlee/Janlee.html		programming languages, compiler design, industry standards, software engineering, history of computing, computer ethics dblp
Peter Lee	Professor Carnegie Mellon U cs.cmu.edu/~petel		design/implementation/foundations of programming languages, language-based computer security, code certification and proof-carrying code, functional programming, formal semantics, type theory dblp
Ruby B. Lee	Professor Princeton U, EE ee.princeton.edu/~rblee		multimedia ISA, media processors and microarchitecture, secure information processing, processor architecture dblp
Sang-Jeong Lee	Professor Soonchunhyang U, Asan, Korea sjlee.sch.ac.kr/Default_eng.htm		ILP, optimizing compilers, value prediction dblp
Thomas H. Lee	Professor Stanford U, ECE www-smirc.stanford.edu/people.html		gigahertz-speed wireline, wireless integrated circuits, high-speed analog circuitry dblp
Miriam Leeser	Professor Northeastern U ECE ece.neu.edu/faculty/leeser.html		FPGA design and applications, Computer Arithmetic, Hardware/Software interfacing dblp
Charles Lefurgy	research staff member IBM Austin research.ibm.com/people/l/lefurgy		low energy computing, code compression dblp
K. Rustan M. Leino	Microsoft Research research.microsoft.com/~leino		programming tools, ESC/Java dblp
Charles E. Leiserson	Professor MIT supertech.lcs.mit.edu/~cel		Cilk, retiming, algorithms, supercomputing, interconnection networks, parallel computation dblp
Guy G. Lemieux	Professor U of British Columbia ECE, Canada ece.ubc.ca/~lemieux		multiprocessors, FPGAs dblp
Philip H. W. Leong	Professor Chinese University of Hong Kong cse.cuhk.edu.hk/~phwl		reconfigurable computing, digital systems, parallel computing, cryptography, signal processing dblp
Xavier Leroy	Senior Researcher INRIA, France cristal.inria.fr/~xleroy		type systems, module systems and static analyses, Ocaml, Linux threads dblp
Rainer Leupers	Professor Technische U Aachen, Germany iss.rwth-aachen.de/1_institut/dok/leupers.htm		embedded software tools, compilers for DSP and VLIW and network processors, code optimization, retargetable compilation, processor architecture dblp
Benjamin A. Levine	Professor U of Pittsburgh, ECE engr.pitt.edu/electrical/people/levine_benjamin.html		reconfigurable computing, high-level synthesis dblp
Steven P. Levitan	Professor U of Pittsburgh, EE kona.ee.pitt.edu/steve		CAD for free space optoelectronic, optoelectronic computing systems, VHDL simulation and synthesis, timing verification, design frameworks, VLSI architectures, parallel algorithm design dblp
Henry M. Levy	Professor U of Washington Seattle, CS cs.washington.edu/homes/levy		SMT, operating systems, Web dblp
David Lewis	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~lewis		computer arithmetic, VLSI design, Transmogrifier, hierarchical FPGA architectures dblp
E. Christopher Lewis	Professor U of Pennsylvania cis.upenn.edu/~eclewis		compilers and programming languages, computer architecture, programming systems for scalable parallel machines dblp
Kai Li	Professor Princeton U, CS cs.princeton.edu/~li		PRISM, SHRIMP, extensible router, scalable I/O dblp
Zhiyuan Li	Professor Purdue U, CS cs.purdue.edu/people/li		optimizing compilers, interface between compilers and OS, performance evaluation of concurrent systems dblp
David J. Lilja	Professor U of Minesotta, EE www-mount.ee.umn.edu/~lilja/lilja.html		high-performance computer architecture, parallel processing, computer systems performance analysis, exploiting hardware-software interactions dblp
Sung Kyu Lim	Professor Georgia Tech, ECE users.ece.gatech.edu/~limsk		physical design automation algorithms and tools for 3D circuits and packages, quantum circuits, FPGA/FPCA/FPAA based reconfigurable systems dblp
Calvin Lin	Professor U of Texas, Austin, CS cs.utexas.edu/users/lin		compilers and languages, parallelism and scientific computing dblp
Christoph Lindemann	Professor Dortmund U, Germany rul-www.cs.uni-dortmund.de/~Lindemann/main.html		Petri nets, performance evaluation dblp
Daniel T. Ling	Corporate Vice President Microsoft Corp. microsoft.com/presspass/exec/ling/default.asp		user interfaces, computer graphics, video RAM, IBM America dblp
Dimitris Lioupis	Professor U of Patras, Greece aiolos.cti.gr/~lioupis		caches, microprocessor design, multimedia architectures dblp
Mikko H. Lipasti	Professor U of Wisconsin-Madison, ECE ece.wisc.edu/~mikko		value prediction, computer architecture, ILP, compiler optimization, runtime systems, operating systems dblp
G. Jack Lipovski	Professor U of Texas at Austin, ECE engr.utexas.edu/news/facstaff/pages/lipovski.cfm		artificial intelligence, computer architectures, microcomputers dblp
Dake Liu	Professor Linkoping U, Sweden isy.liu.se/~dake		system on chip integration, Application Specific Instruction set Processors (ASIP), DSP processors and accelerators, communication ASICs dblp
Yanhong Annie Liu	Professor State U of NY at Stony Brook, CS cs.sunysb.edu/~liu		programming languages, compilers and software systems, program analysis and transformation for incremental/parallel/concurrent computation, optimizing compilers dblp
Josep Llosa	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/josepll		hardware and compiler support for ILP dblp
Jien-Chung Lo	Professor U of Rhode-Island ele.uri.edu/faculty/lo.html		fault-tolerant computing, distributed networked computing, reliable logic circuit designs, VLSI testing dblp
Gabriel H. Loh	Professor Georgia Tech, CS cc.gatech.edu/~loh		high-performance processor microarchitecture, branch prediction dblp
Ronald J. Lomax	Professor (emeritus) U of Michigan www-personal.engin.umich.edu/~rjl		processor design dblp
Rita Loogen	Professor Philipps-Universitat, Marburg, Germany mathematik.uni-marburg.de/~loogen		declarative parallel programming, integration of functional and logic programming languages, parallel implementation of functional languages dblp
P. Geoffrey Lowney	Director, Compiler and Architecture Advanced Development Intel Architecture Group intel.com/pressroom/kits/bios/plowney.htm		compilers for Alpha and Itanium, Multiflow, Spike dblp
Shih-Lien Lu	Intel MRL ece.orst.edu/~sllu (old)		counterflow pipelines, self-timed circuits and systems design, VLSI systems, computer arithmetic, computer architecture dblp
Yung-Hsiang Lu	Professor Purdue U, ECE ece.purdue.edu/~yunglu		energy-efficient and low-power systems, operating systems, wireless applications, reconfigurable architectures, VLSI design automation, embedded systems dblp
David Luick	IBM Rochester		VLIW
Chi-Keung Luk	Intel cs.cmu.edu/~luk (old)		data prefetch for pointer code dblp
Wayne Luk	Senior lecturer Imperial College, London, UK doc.ic.ac.uk/~wl		run-time reconfigurable architectures, library-based compilation techniques dblp
Steven Lumetta	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~steve		high-performance networking and computing, hierarchical systems, parallel runtime software dblp
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Enrico Macii	Professor Politecnico di Torino, Italy eda.polito.it/enrico.html		CAD of digital integrated circuits and systems, logic synthesis/optimization/testing/formal verification, power estimation and optimization dblp
Kenneth M. Mackenzie	Adjunct Professor Georgia Tech U/Reservoir Labs cc.gatech.edu/~kenmac		Fugu, Alewife, soft architectures, active system-area networks dblp
David B. MacQueen	Professor U of Chicago cs.uchicago.edu/people/dbm		programming language design/definition/implementation, type and module systems, SML/NJ dblp
Tara M. Madhyastha	Professor UC Santa Cruz cse.ucsc.edu/~tara		high-bandwidth I/O interfaces, automatic performance characterization and adaptation dblp
Vijay K. Madisetti	Professor Georgia Tech, ECE users.ece.gatech.edu/~vkm/home.html		DSP, rapid prototyping, signal processors, VLSI CAD dblp
Bruce M. Maggs	Professor Carnegie Mellon U, CS cs.cmu.edu/~bmm		interconnection networks, parallels algorithms dblp
Nihar R. Mahapatra	Professor State U of New York at Bufallo cse.buffalo.edu/~mahapatr		computer architecture, parallel processing, VLSI, fault tolerance dblp
Rabi N. Mahapatra	Professor Texas A&M U, CS cs.tamu.edu/faculty/rabi		parallel and distributed computing, computer architecture, embedded system codesign dblp
Scott A. Mahlke	U of Michigan eecs.umich.edu/~mahlke		Trimaran, Elcor, EPIC, application-specific processor design, compilers, computer architecture, high-level synthesis dblp
Wai-Kei Mak	Professor National Tsing Hua U, Taiwan cs.nthu.edu.tw/~wkmak		VLSI CAD, discrete optimization, combinatorial optimization, computer architecture dblp
Miroslaw Malek	Professor Humboldt U Berlin, Germany informatik.hu-berlin.de/~malek		high-performance responsive computing, parallel architectures, real-time systems, networks, fault tolerance dblp
Sharad Malik	Professor Princeton U, EE ee.princeton.edu/~sharad/		CAD, Electronic Design Automation, design tools for embedded systems, hardware-software integration, digital circuit theory, synthesis and verification of digital systems dblp
Wojciech P. Maly	Professor Carnegie Mellon U, ECE ece.cmu.edu/~maly		VLSI design testing and manufacturing dblp
William H. Mangione-Smith	Professor UC Los Angeles icsl.ucla.edu/~billms		configurable computing systems, low power processor and system design, multimedia and communications processing, instruction-level parallelism, Mediabench dblp
Rajit Manohar	Professor Cornell U, ECE vlsi.cornell.edu/~rajit		asynchronous VLSI design, low energy design, architecture, concurrency, formal methods, programming language semantics, information theory dblp
Elias S. Manolakos	Professor Northeastern U, ECE cdsp.neu.edu/info/faculty/manolakos/manolakos.html		high performance computing, synthesis of parallel algorithms and architectures, pattern recognition and neural networks dblp
Panagiotis Manolios	Professor Georgia Institute of Technology cc.gatech.edu/~manolios		formal verification, theorem proving, model checking, abstraction, algorithms dblp
Olivier Maquelin	postdoc McGill U, Montreal, Canada cs.mcgill.ca/~maquelin (old)		multithreaded systems, EARTH dblp
Diana Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~dianam		energy-aware computing, low power CAD dblp
Radu Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~radum		embedded systems, low-power CAD dblp
Malgorzata Marek-Sadowska	Professor U of California at Santa Barbara, ECE ece.ucsb.edu/Faculty/Marek-Sadowska/default.html		VAD for layout and logic synthesis, simulation of nonlinear circuits, timing verification dblp
Darko Marinov	Professor U of Illinois at Urbana-Champaign CS cag.lcs.mit.edu/~marinov		specification languages, checking code conformance, compilers, correctness of analyses and optimizations dblp
Evangelos P. Markatos	Professor U of Crete, Grece ics.forth.gr/~markatos		systems software for large scale multiprocessros, Psyche multiprocessor OS dblp
Igor L. Markov	Professor U of Michigan eecs.umich.edu/~imarkov		design of integrated circuits, quantum computing dblp
Marco Ajmone Marsan	Professor Politecnico di Torino, Italy www1.tlc.polito.it/ajmone		high-speed telecommunication networks, wireless and all-optical networks, performance evaluation of data communication and computer systems, Markovian models, queuing networks, generalized stochastic Petri nets dblp
Alain J. Martin	Professor Caltech U, CS cs.caltech.edu/cspeople/faculty/martin_a.html		asynchronous VLSI dblp
Milo M. K. Martin	Professor U of Pennsylvania cis.upenn.edu/~milom		computer architecture, multiprocessors, memory coherence dblp
Jose F. Martinez	Professor Cornell U, ECE csl.cornell.edu/~martinez		parallel computer architecture dblp
Margaret Martonosi	Professor Princeton U, EE ee.princeton.edu/~mrm		cache-decay, cache-miss equations, reconfigurable hardware (SAT) dblp
Peter Marwedel	Professor U of Dortmund, Germany ls12-www.cs.uni-dortmund.de/~marwedel		compilers for embedded processors, embedded software, high-level synthesis, test program generation for processors dblp
Peter M. Maurer	Professor U of South Florida csee.usf.edu/~maurer		VLSI design automation, VLSI design, software testing, computer architecture, parallel processing, FHDL, DGL dblp
John D. McCalpin	Senior Scientist IBM, Austin home.austin.rr.com/mccalpin		memory bandwidth, STREAM benchmark
Joel McCormack	Hewlett Packard WRL research.compaq.com/wrl/people/joel/bio.html		computer graphics, CAD dblp
Scott McFarling	Microsoft Research research.microsoft.com/~smcfar		profile-based optimization of memory performance, branch prediction dblp
Sally A. McKee	Professor Cornell U ECE csl.cornell.edu/~sam		processor and memory systems architecture, embedded systems, compilers, operating systems, performance analysis techniques and tools, Impulse dblp
Nick McKeown	Professor Stanford U, EE klamath.stanford.edu/~nickm		Tiny Tera, packet switches dblp
Kathryn S. McKinley	Professor U of Texas, Austin, CS cs.utexas.edu/users/mckinley		compilers, ParaScope dblp
Kenneth L. McMillan	Researcher Cadence Berkeley Labs www-cad.eecs.berkeley.edu/~kenmcmil		formal verfication, symbolic model checking, SMV dblp
Carver A. Mead	Professor (emeritus)/Chairman Caltech U/Foveon foveon.com/about_executive.html Allen Newel (1997) award, von Neumann Medal		semiconductors, physics of computation dblp
Eduard Mehofer	Professor U of Viena, Austria par.univie.ac.at/~mehofer		optimising compilers, parallel and distributed computing, communication optimizations, feedback-directed compilation, grid computing dblp
Nagi N. Mekhiel	Professor Ryerson Polytechnic U, Canada ee.ryerson.ca/~nmekhiel		computer architecture and parallel processing, high performance memory systems, VLSI, performance evaluation
Waleed M. Meleis	Professor Northeastern U, ECE ece.neu.edu/faculty/meleis.html		code scheduling dblp
Rami G. Melhem	Professor U of Pittsburgh, CS cs.pitt.edu/~melhem		fault-tolerant systems, optical networks, real-time parallel and distributed systems, power aware computing dblp
John M. Mellor-Crummey	Professor Rice U, CS cs.rice.edu/~johnmc		software support for HCP, multiprocessor synchronization, parallel debugging, parallel operating systems, parallelizing compilers, compiler and run-time techniques for improving memory hierarchy performance dblp
Gokhan Memik	Professor Northwestern U ECE ece.northwestern.edu/~memik		application-specific programmable processors, compilers, embedded systems, microarchitecture dblp
Oskar Mencer	Professor Imperial College, UK/Bell Labs, Lucent doc.ic.ac.uk/~oskar/		general computer architecture, custom computing, FPGAs, computer arithmetic, domain-specific compilers, low-power computing, CAD and VLSI dblp
Bilha Mendelson	Manager, Code optimization group IBM Research Lab, Haifa, Israel		code optimization, compiler optimization, modern computer architecture dblp
Teresa H. Meng	Professor Stanford U, ECE dualist.stanford.edu/~thm		low-power circuit and system design, video signal processing, wireless communications, circuit optimization, neural signal processing, computation architectures for future CMOS technology, Atheros Communications dblp
José Meseguer	Professor U of Illinois at Urbana-Champaign, CS formal.cs.uiuc.edu/meseguer/		declarative languages, OBJ, Maude, formal specification and verification, concurrency theory, parallel software and architectures for declarative languages, logical foundations of computer science dblp
David G. Messerschmitt	Professor UC Berkeley, ECE eecs.berkeley.edu/~messer		technology/economy/business, DSP, networking, VLSI, signal processing dblp
David G. Meyer	Professor Purdue U, ECE digibowser.ecn.purdue.edu/dsl/meyer.html		instructional multimedia, technology-based education, computer architecture and parallel processing, microprocessor system design and interfacing, electro-acoustics dblp
Dirk Meyer	senior vice president AMD corp. Maurice Wilkes (2003) award		Athlon, Opteron, Alpha 21064, 21264
Maged M. Michael	IBM T. J. Watson cs.rochester.edu/u/michael (old)		distributed shared memory dblp
Pierre Michaud	Researcher IRISA, France irisa.fr/caps/people/michaud/index_fr.htm		computer architecture dblp
Giovanni De Micheli	Professor Stanford U, ECE akebono.stanford.edu/users/nanni		CAD, digital circuits, hw/sw codesign, VLSI dblp
Samuel P. Midkiff	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~smidkiffw		high performance compilers, programming environments and tools, compilation of explicitly parallel programs, utility of consistency models, compiling for safety and repeatability, Polaris, Numeric Java dblp
Robin Milner	Professor U of Cambridge, UK cl.cam.ac.uk/users/rm135 Turing (1991) award		LCF, ML, CCS dblp
Veljko M. Milutinovic	Professor U of Belgrade, Serbia, Yugoslavia galeb.etf.bg.ac.yu/~vm		Internet, infrastructure for Electronic Business on Internet, SMP and DSM, VLSI, microprocessor architecture/design, FPGA, silicon compilation dblp
Jayadev Misra	Professor U of Texas, Austin, CS cs.utexas.edu/users/misra		formal methods, specifications/designs of synchronous/asynchronous systems, UNITY dblp
Markus U. Mock	Professor U of Pittsburgh, CS cs.pitt.edu/~mock		compilers and computer architecture, (run-time) program optimization, static and dynamic program analysis dblp
Adrian Moga	Sequent Computer Systems Inc usc.edu/dept/ceng/dubois/moga/moga.html (old)		DSM, hardware emulation dblp
Saraju P. Mohanty	Professor U of North Texas cs.unt.edu/~smohanty		CAD for nanoscale VLSI, synthesis and optimization for low power, power-aware system design, VLSI architectures for security and DRM dblp
Aloysius K. Mok	Professor U of Texas at Austin cs.utexas.edu/users/mok		fault-tolerant hard-real-time systems, system architecture, computer-aided system design tools, software engineering dblp
Dan I. Moldovan	Professor U Texas at Dallas utdallas.edu/~moldovan		systolic processors, natural language processing, machine learning, artificial intelligence, parallel and distributed processing dblp
Charles E. Molnar	(deceased) U of Washington in St. Louis /www.cse.wustl.edu/history/molnar_c		asynchronous circuits, metastability, LINC, audio signals and neural responses, biomedical computing dblp
Burkhard Monien	Professor U Paderborn, Germany uni-paderborn.de/fachbereich/AG/monien/PERSONAL/bm.html		parallel computation, parallel architecture, scientific computing, interconnection networks dblp
Soo-Mook Moon	Professor Seoul National U, Korea ee.snu.ac.kr/english/faculty/moon-soomook.htm		system software, microprocessor structure, superpipelining dblp
Oege de Moor	Professor Oxford U, UK web.comlab.ox.ac.uk/oucl/people/oege.demoor.html		intentional programming, transformation of Haskell programs, algebra of programming, predicate transformers, compositional logic programming, complexity and programming languages dblp
Gordon E. Moore	Chairman Emeritus of the Board Intel developer.intel.com/pressroom/kits/bios/moore.htm		Moore's law, Intel dblp
J. Strother Moore	Professor U of Texas, Austin, CS cs.utexas.edu/users/moore		theorem prooving, Boyer-Moore theorem prover, hardware and software verification, ACL2 dblp
Edward David Moreno	Professor U of Sao Paulo, Brazil lsi.usp.br/~edmoreno		computer architecture, performance evaluation and analysis, Petri nets, computer networks, reconfigurable hardware dblp
Jaime H. Moreno	IBM T. J. Watson		processor architecture, ILP, embedded systems, systolic matrix computations dblp
Csaba Andras Moritz	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/andras		Cool-*: compiler-enabled power-aware microprocessor architecture, self-evolving software/hardware dblp
John Morris	Professor U of Western Australia ciips.ee.uwa.edu.au/~morris		high performance parallel processors, reconfigurable processors, networks of workstations, fault-tolerant Cilk, Achilles high-bandwidth interconnect, asynchronous logic, software verification dblp
Andreas Moshovos	Professor U of Toronto, EE, Canada eecg.toronto.edu/~moshovos		PACT, SHARPP, slice processors, memory dependence speculation dblp
J. Eliot B. Moss	Professor U of Massachusetts, Amherst www-osl.cs.umass.edu/~moss		programming language design and implementation, database and information retrieval systems, persistent object stores and persistent programming languages, memory management and garbage collection dblp
Todd C. Mowry	Professor Carnegie Mellon U, CS cs.cmu.edu/~tcm		Thread-Level Data Speculation, Stampede, software prefetching dblp
Steven S. Muchnick			compilers dblp
Trevor N. Mudge	Professor U of Michigan eecs.umich.edu/~tnm		PowerAnalyzer, instruction stream compression, microprocessor verification, high performance computing dblp
Frank Mueller	Professor North Carolina State U moss.csc.ncsu.edu/~mueller		compilers, real-time systems, parallel and distributed systems dblp
Silvia M. Mueller	U des Saarlandes, Germany www-wjp.cs.uni-sb.de/~smueller		complexity and correctness of computer architectures, parallel architectures: design / modelling / performance, parallelization of algorithms, hardware support for multimedia dblp
Shubhendu S. Mukherjee	Hewlett Packard cs.wisc.edu/~shubu/shubu.html (old)		network interfaces, coherence protocols dblp
Hans Mulder	Senior Principal Engineer Intel Research intel.com/research/people/bios/mulder_h.htm		Itanium, distributed systems, ubiquitous computing dblp
Henk Muller	Reader U of Bristol, UK cs.bris.ac.uk/~henkm		data diffusion machine, trivial mobile software, PRISMA, DOOM dblp
Jean-Michel Muller	senior researcher Ecole Normale Superieure de Lyon, France ens-lyon.fr/~jmmuller		algorithms and architectures for fast and/or accurate arithmetic, number systems, elementary functions, Cordic dblp
Markus Müller-Olm	Research assistant Dortmund U, Germany sunshine.cs.uni-dortmund.de/~mmo		analysis and verification of programs and systems dblp
Kazuaki Murakami	Professor Kyushu U, Japan kasuga.csce.kyushu-u.ac.jp/~murakami		computer system architecture, parallel computing/processing, compiling for parallel architectures, performance evaluation, architecture/hardware modeling and optimization dblp
Saburo Muroga	Professor (emeritus) U of Illinois Urbana-Champaign, ECE cs.uiuc.edu/contacts/faculty/muroga.html		CAD, Transduction, SYLON dblp
Chris J. Myers	Professor U of Utah, ECE shang.elen.utah.edu/~myers		design methods and tools for VLSI systems, asynchronous circuit design, formal timing verification, design of analog decoders dblp
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David Nagle	Research Scientist Carnegie Mellon U, ECE ece.cmu.edu/~bassoon		Active storage, MEMS storage, NASD dblp
Walid A. Najjar	Professor UC Riverside, CS cs.ucr.edu/~najjar		reconfigurable computing, Cameron, multithreaded and parallel architectures and compilation techniques, interconnection networks and router architectures, SA-C dblp
Farid N. Najm	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~najm		CAD tool for low-power and reliable VLSI circuits, high-level power modeling and estimation, low-power design, reliability analysis and prediction, CAD for SOI circuits dblp
Ashwini K. Nanda	Manages, Scalable Server Architecture Group IBM T. J. Watson research.ibm.com/people/a/ashwini		computer architecture, shared memory system design and performance dblp
Lasse Natvig	Professor Norwegian U of Science and Technology, Norway idi.ntnu.no/~lasse		computer architecture, parallel algorithms, architectures and programming, theoretical models of parallel computation, simulation of computer systems dblp
George C. Necula	Professor UC Berkeley, CS cs.berkeley.edu/~necula		Proof-Carrying Code (PCC), certifying compilation, translation validation dblp
Brent E. Nelson	Professor Brigham Young U, EE ee.byu.edu/faculty/nelson		hardware design and CAD, reconfigurable computing, VLSI design, Teramac dblp
John von Neumann	(deceased) Princeton U nationalacademies.org/history/members/neumann.html		von Neumann architecture, stored program concept, reliability theory, logic design, self-reproducing automata dblp
Lionel M. Ni	Professor Michigan State U mcast.cps.msu.edu/ni		local network, VLSI design automation, parallel compilers, computer system performance evaluation, fault-tolerant computing, parallel machines, cut-through switch architecture dblp
Alexandru Nicolau	Professor UC Irvine ics.uci.edu/~nicolau		paralellizing compilers, embedded systems dblp
Michael T. Niemier	Professor Georgia Tech, CS cc.gatech.edu/~mniemier		computer architecture, quantum celular automata dblp
Rishiyur S. Nikhil	Sandburst Corporation		*T, P-RISC, multithreading, ASIC design in high-level languages dblp
David Notkin	Professor U of Washington Seattle, CS cs.washington.edu/homes/notkin/		dynamic detection of program invariants, symbolic model checking for software specifications, software engineering dblp
Andreas G. Nowatzyk	Professor Carnegie Mellon U, ECE cs.cmu.edu/~agn		single-chip multiprocessors, 3D cellular automata dblp
Steven M. Nowick	Professor Columbia U, CS cs.columbia.edu/~nowick		asynchronous digital circuits, VLSI CAD, low-power and high-performance digital design, logic synthesis, formal hardware verification dblp
Jari Nurmi	Professor U of Tampere, Finland cs.tut.fi/~nurmi		DSP, digital communication systems-on-chip dblp
Kristen Nygaard	(deceased) Oslo U, Norway ifi.uio.no/~kristen Turing (2001) award, von Neumann Medal (2001)		Simula, object-oriented programming dblp
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Robert O'Callahan	Novell cs.cmu.edu/~roc (old)		context-sensitive alias analysis using types, Mozilla, multithreaded program analysis, race detection dblp
Ciaran O'Donnell	Systems Software Consultant Joseph Media Tools, Santa Clara, CA josephmediatools.com/album1_003.htm		compilers, architecture simulation dblp
David O'Hallaron	Professor Carnegie Mellon U, CS cs.cmu.edu/~droh		Quake, Warp, HPC, Fx dblp
John O'Leary	senior engineer Strategic CAD Labs, Intel		formal hardware verification and specification dblp
Stuart F. Oberman	Principal Engineer NVIDIA oberman.net		floating-point division, computer arithmetic dblp
Martin Odersky	Professor Ecole Polytechnique Federale de Lausanne, Switzerland lampwww.epfl.ch/~odersky		object-oriented and functional programming, Scala dblp
Vojin G. Oklobdzija	Professor UC Davis, ECE ece.ucdavis.edu/acsel		high-speed digital circuits, VLSI arithmetic and development of fast structures, design for low-power, high-performance system architecture, design methodology for testability and reliability dblp
Ken Olsen	computerhistory.org/events/hall_of_fellows/olsen		minicomputer, Digital Equipment Corp.
Kunle Olukotun	Professor Stanford U, CS ogun.stanford.edu/~kunle		Hydra, system-level design dblp
Amos Omondi	Professor Flinders U, Adelaide, Australia infoeng.flinders.edu.au/people/pages/omondi_amos		computer architecture, multimedia processors, computer arithmetic dblp
Soner Önder	Professor Michigan Tech U, CS cs.mtu.edu/~soner		computer architecture, programming languages dblp
Tamiya Onodera	IBM Research Tokio trl.ibm.com/people/onodera		efficient implementation of object-oriented programming languages dblp
Alex Orailoglu	Professor UC San Diego, CS cs.ucsd.edu/users/alex		Electronic Design Automation, VLSI testing, Synthesis of fault-tolerant ICs dblp
Mark Oskin	Professor U of Washington, Seattle, CS cs.washington.edu/homes/oskin		computation cache, quantum computer architecture, active pages dblp
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David A. Padua	Professor U of Illinois Urbana-Champaign, CS polaris.cs.uiuc.edu/~padua		computer architecture and systems, parallel computing, POLARIS dblp
Yunheung Paek	Professor Seoul National U ECE, Korea compiler.snu.ac.kr		rapid ASIP prototyping, compiler optimizations for network processors, automatic parallelization PC clusters dblp
Ian Page	Reader Oxford U, UK doc.ic.ac.uk/~ipage		Handel-C, hardware compilation dblp
Vijay S. Pai	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~vpai/		multiprocessors, high-performance system architecture dblp
Subbarao Palacharla	Desktop Platforms Group, Intel Corporation		complexity-effective superscalar dblp
Krishna V. Palem	Professor Georgia Tech U, ECE ece.gatech.edu/faculty/fac_profiles/bio.php?empno=504573		adaptive hardware, compiler optimizations for ILP, embedded and fault-tolerant systems, parallel computing, programmable memory hierarchies, smart caches, real-time systems, string and pattern matching, Trimaran dblp
Jens Palsberg	Professor UC Los Angeles, CS cs.ucla.edu/~palsberg		type inference for object-oriented software, interoperability of software systems, high assurance for embedded software, type-based analysis and applications dblp
David Z. Pan	Professor U of Texas at Austin ECE ece.utexas.edu/~dpan		VLSI CAD, physical design, low power, design for manufacturability dblp
Dhabaleswar K. Panda	Professor Ohio State U cis.ohio-state.edu/~panda		parallel computer architecture, wormhole routing, interprocessor communication, DSM, HPC, clustered and heterogeneous systems, quality of service, resource management dblp
Santosh Pande	Professor Georgia Tech U, CS cc.gatech.edu/~santosh		compiler optimizations for embedded and configurable systems dblp
Greg Papadopoulos	vice president, CTO Sun sun.com/aboutsun/media/ceo/mgt_papadopoulos.html		scalable systems, multithreaded/dataflow processor architecture, functional and declarative languages, fault-tolerant computing dblp
Efstathios Papaefstathiou	Microsoft Research, Cambridge, UK research.microsoft.com/users/efp		analytical and hybrid performance modeling methodologies and tools, parallel programming paradigms and development tools, software performance engineering, Indy dblp
Marios C. Papaefthymiou	Professor U of Michigan eecs.umich.edu/~marios		computer system design, energy and timing, parallel and distributed computing dblp
Corina S. Pasareanu	NASA Ames ase.arc.nasa.gov/people/pcorina		formal software verification, program abstraction, modular reasoning dblp
Nikolaos P. Paschalidis	Space Department, John Hopkins U		analog digital microlectronics, sensors and microsystems for space instruments and spacecraft avionics, space physics
Janak H. Patel	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?jhpatel		computer architecture, testing and fault-tolerance dblp
Sanjay J. Patel	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~sjp		processor microarchitcture, computer architecture, high performance, reliable computer systems, trace cache dblp
Yale N. Patt	Professor U of Texas, Austin, ECE ece.utexas.edu/~patt Eckert-Mauchly (1996) award		HPS, two-level branch prediction, computer architecture dblp
David A. Patterson	Professor UC Berkeley, CS cs.berkeley.edu/~pattrsn von Neumann Medal (2000)		RISC, RAID dblp
Donald O. Pederson	(deceased) UC Berkeley berkeley.edu/news/media/releases/2005/01/05_donpederson.shtml		SPICE dblp
Li-Shiuan Peh	Professor Princeton U, EE ee.princeton.edu/~peh		interconnection networks dblp
Doron A. Peled	Professor University of Warwick, UK dcs.warwick.ac.uk/~doron		concurrency theory, formal verification, formal specification, semantics of programming languages, model checking, finite automata, software testing, temporal logics, partial order methods, traces dblp
Ronald H. Perrott	Professor Queen's University Belfast, United Kingdom cs.qub.ac.uk/~R.Perrott		Grid Computing, software engineering, design and implementation of parallel programming languages, high performance computing and support tools, Design/construction/analysis of algorithms dblp
Erez Petrank	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~erez		cryptography, garbage collection, computational complexity dblp
Frank Pfenning	Professor Carnegie Mellon U, CS cs.cmu.edu/~fp		programming languages, logic and type theory, logical frameworks, automated deduction dblp
Michael Philippsen	Professor U Erlangen-Nürnberg, Germany www2.informatik.uni-erlangen.de/~phlipp		compilers for Java dblp
Christian Piguet	head of the ultra-low-power sector Centre Suisse d'Electronique et de Microtechnique		very low-power microprocessors, low-power standard cell libraries, gated clock and low-power techniques, asynchronous design dblp
Lawrence T. Pileggi	Professor Carnegie Mellon U, ECE ece.cmu.edu/~pileggi		delay metrics, clock distribution and design, interconnects, timing analysis dblp
Keshav K. Pingali	Professor Cornell U, CS cs.cornell.edu/annual_report/pingali.htm		High Performance Computing, compilers, program analysis dblp
Timothy M. Pinkston	Professor U of Southern California usc.edu/dept/ceng/pinkston/people/pinkston.html		high-performance interconnection networks for multiprocessors, performance analysis, optical interconnection networks, parallel processing dblp
Nikos P. Pitsianis	Professor Duke U, CS cs.duke.edu/~nikos		numerical linear algebra and parallelization, symbolic and compiler optimization, FFTs, wavelets, simulation, high performance and scientific computing dblp
Marco Platzner	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~platzner		reconfigurable computing, hardware/software codesign, embedded systems dblp
Andrew R. Pleszkun	Professor U of Colorado, ECE ece-www.colorado.edu/faculty/pleszkun.html		computer architecture dblp
Dionisios N. Pnevmatikatos	Professor Technical U of Crete, Grece ics.forth.gr/~pnevmati		VLSI design and implementation of processors and network switches, ILP processor architectures: instruction fetching/predicated execution/compilation techniques, systems design: memory/disk/clusters of workstations dblp
Amir Pnueli	Professor Weizmann Institute, Israel wisdom.weizmann.ac.il/~amir Turing (1996) award		formal verification dblp
Fred J. Pollack	Director Intel Microprocessor Research Labs developer.intel.com/pressroom/kits/bios/fpollack.htm		Pentium Pro, i960, operating systems dblp
Constantine D. Polychronopoulos	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?cdp		compilers and operating systems, parallel and distributed computing, wireless networks and mobile computing dblp
Dmitry V. Ponomarev	Professor U of Binghampton CS cs.binghamton.edu/~dima/		energy efficient design, high-end microprocessors dblp
Viktor Prasanna	Professor U of Southern California ceng.usc.edu/~prasanna		high performance computing, parallel and distributed systems, network computing, embedded systems dblp
Ian A. Pratt	Senior lecturer U of Cambridge Computer Laboratory, UK cl.cam.ac.uk/users/iap10		computer architecture, networking, operating systems, Xen dblp
Milos Prvulovic	Professor Georgia Tech, CS cc.gatech.edu/~milos		computer architecture, architectural support for programmability and productivity, fault tolerance and recovery, thread-level speculation dblp
William Pugh	Professor U of Maryland, CS cs.umd.edu/~pugh		skip lists, Omega test, algorithms and data structures, automatic parallelization, dependence analysis, Java dblp
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Bin Qiu	Professor Monash U csse.monash.edu.au/research/avipac/njnf/staff_profiles/profile_bq.htm		signal processing, network QoS and congestion control, network traffic modelling and prediction, communication electronics and computer architecture, video and image processing dblp
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Jan M. Rabaey	Professor UC Berkeley, EE bwrc.eecs.berkeley.edu/People/Faculty/jan		digital integrated circuits, low-power design dblp
Sriram K. Rajamani	Microsoft Research research.microsoft.com/~sriram		model checking, static analyses, SLAM dblp
Ryan Rakvic	Intel ece.cmu.edu/~rnr (old)		memory hierarchy optimizations dblp
Umakishore Ramachandran	Professor Georgia Tech U, CS cc.gatech.edu/~rama		Clouds, Beehive, Stampede dblp
G. Ramalingam	IBM T. J. Watson research.ibm.com/people/r/rama/		static analysis, compilers dblp
C. V. Ramamoorthy	Professor (emeritus) UC Berkeley, CS cs.berkeley.edu/People/Faculty/Homepages/ramamoorthy.html		distributed systems, Petri nets, software engineering, databases dblp
J. Ramanujam	Professor Louisiana State U ece.lsu.edu/jxr		compiler optimizations, embedded systems, low-power computing, high performance computing, hardware synthesis, configurable computing, computer architecture, operating systems, distributed systems dblp
Alex Ramirez	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/aramirez		fetch engine performance, commercial workloads, compiler optimizations, binary translation, architecture simulation dblp
Norman Ramsey	Professor Harvard U eecs.harvard.edu/~nr		C--, SLED, Zephyr, retargetable debugger, noweb (literate programming) dblp
Nagarajan Ranganathan	Professor U of South Florida vcapp.csee.usf.edu/~ranganat		VLSI Algorithms and architectures, application specific VLSI system design, VLSI design automation, data compression, VLSI for image/video/signal processing, computer architecture and parallel computing dblp
Parthasarathy Ranganathan	Hewlett Packard WRL research.compaq.com/wrl/people/parthas/bio.html		computer architecture, parallel computing, performance evaluation, low-power system design dblp
Srikantam Sai Surya Prakasa Rao	Professor Indian Institute of Technology, Bombay, India cse.iitb.ac.in/~ssspr/personal.html		VLSI Design, computer architecture, reconfigurable computing, microprocessor design and interfaces dblp
Justin R. Rattner	director Microprocessor Research, Intel intel.com/pressroom/kits/bios/jrattner.htm		ASCII Red, advanced circuits, microarchitecture, architecture dblp
Bob Ramakrishna Rau	(deceased) Hewlett-Packard Labs trimaran.org/car_group/bob_rau.html Eckert-Mauchly (2002) award		VLIW, EPIC, Elcor, Trimaran, PICO, rotating register files, Cydra 5 dblp
Lawrence Rauchwerger	Professor Texas A&M U, CS cs.tamu.edu/faculty/rwerger		speculative parallelization, Polaris dblp
Daniel A. Reed	Professor U of Illinois at Urbana-Champaign, CS www-pablo.cs.uiuc.edu/People/Reed/DanReed.htm		performance analysis techniques and resource management for parallel systems dblp
John Regehr	Professor U of Utah, CS cs.utah.edu/~regehr		embedded systems dblp
Jakob Rehof	Microsoft Research research.microsoft.com/~rehof		type systems, type inference, model checking and type systems for concurrent programs, static program analysis, program logics, complexity and scalability of program analyses dblp
Steven K. Reinhardt	Professor U of Michigan eecs.umich.edu/~stever		computer architecture, parallel and distributed systems, operating systems, computer system simulation dblp
Glenn Reinman	Professor UC Los Angeles cs.ucla.edu/~reinman		computer architecture, ILP, speculative execution, branch prediction and fetch architectures, cache design and prefetching, CACTI, scalable architectures dblp
Didier Rémy	Researcher INRIA Rocquencourt, France pauillac.inria.fr/~remy/		type systems and type inference, object oriented languages, concurrent and distributed languages, semantics of programming languages, Ocaml, Join dblp
Jose Renau	Professor UC Santa Cruz coe.ucsc.edu/~renau		energy/performance trade-offs, thread level speculation, simulation tools, FPGAs, complexity dblp
John H. Reppy	Professor U of Chicago people.cs.uchicago.edu/~jhr		design and implementation of advanced programming languages, Moby, SML/NJ dblp
Thomas W. Reps	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~reps/reps.html		program slicing, shape analysis, model checking dblp
John C. Reynolds	Professor Carnegie Mellon U, CS cs.cmu.edu/~jcr		design of programming languages, semantics of programming languages, methods for proving that programs meet specifications dblp
Laura Ricci	Professor U of Pisa, Italy di.unipi.it/~ricci		compilation and modelling of HPC, parallelization of irregular applications, static analysis dblp
Martin C. Rinard	Professor MIT cag.lcs.mit.edu/~rinard		commutativity analysis, compilers, multithreaded program analysis dblp
Dennis M. Ritchie	Bell Labs, Lucent cm.bell-labs.com/cm/cs/who/dmr Turing (1983) award		C, Unix dblp
Scott Rixner	Professor Rice U, CS cs.rice.edu/~rixner		microprocessor architecture, media and network processing, VLSI and computer architectures, memory system architecture dblp
Davide Rizzo	ST Microelectronics		architectural support for multimedia dblp
Anne Rogers	Prfessor U of Chicago, CS people.cs.uchicago.edu/~amr		compilers, Olden, parallel programming dblp
Ronny Ronen	Israel Microarchitecture Lab Director Intel intel.com/research/mrl/people/ronen_r.htm		microprocessor architecture and microarchitecture, compilers dblp
Jonathan Rose	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~jayar		FPGAs architecture, CAD, Field-Programmable Systems, graphics and vision applications on FPGAs dblp
Mendel Rosenblum	Professor Stanford U/Vmware simos.stanford.edu/~mendel		SimOS, FLASH, Hive, Disco, log-structured filesystem dblp
Guido van Rossum	Elemental Security python.org/~guido		Python, Amoeba, hypermedia dblp
Grigore Rosu	Professor U of Illinois at Urbana-Champaign, CS gureni.cs.uiuc.edu/~grosu		design/semantics/implementation of programming and specification languages, certification/monitoring/synthesis/modularization, automated reasoning, algorithms, category theory dblp
Eric Rotenberg	Professor North Carolina State U, ECE tinker.ncsu.edu/ericro		Trace cache, Slipstream processors dblp
Amir Roth	Professor U of Pennsylvania cis.upenn.edu/~amir		multithreaded processors, prediction dblp
Jerry Roth	Professor Gonzaga U cps.gonzaga.edu/~roth		optimizing compiler technology for scalar and parallel architectures dblp
Kaushik Roy	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~kaushik		low power VLSI dblp
Elizabeth M. Rudnick	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~liz		design verification, test generation, fault simulation, design for testability, fault diagnosis, VLSI system design, electronic design automation dblp
Larry Rudolph	professor MIT csg.lcs.mit.edu/~rudolph		starT, parallel computation, Oxygen dblp
Erik Ruf	Microsoft Research research.microsoft.com/~ruf		design and implementation of programming languages, Bartok, AST toolkit dblp
Radu Rugina	Professor Cornell U, CS cs.cornell.edu/People/rugina		multithreaded prog. pointer analysis, automatic paralellization dblp
Rob A. Rutenbar	Professor Carnegie Mellon U, ECE ece.cmu.edu/~rutenbar		custom analog circuit CAD, high-performance digital ICs and CAD dblp
Oliver Rüthing	post doc (old) U of Dortmund, Germany ls5-www.cs.uni-dortmund.de/~ruething		static analysis, lazy code motion dblp
Barbara G. Ryder	Professor Rutgers U, CS cs.rutgers.edu/~ryder		compile-time program analyses, tools for program understanding/testing/maintenance, optimization of object-oriented programs, static and dynamic program analyses in server systems dblp
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Shmuel Sagiv	Professor Tel Aviv U, Israel math.tau.ac.il/~msagiv		programming languages, compilers, abstract interpretation, profiling, pointer analysis, interprocedural dataflow analysis, program slicing, porting source code, language-based programming environments dblp
Sartaj K. Sahni	Professor U of Florida cise.ufl.edu/~sahni		data structures and algorithms, scheduling, optimization, VLSI CAD, computational geometry, image processing, medical applications dblp
Pascal Sainrat	U Paul Sabatier, Toulouse, France irit.fr/recherches/ARCHI/MARCH/SAINRAT/ANGLAIS/sainrat.frame.shtm		interconnection networks, superscalar architectures dblp
Suleyman Sair	Professor North Carolina State U ECE cesr.ncsu.edu/ssair		computer architecture, phase-based program analysis and optimizations, adaptive scheduling for VLIW, memory hierarchy design and prefetching dblp
Karem A. Sakallah	Professor U of Michigan eecs.umich.edu/~karem		VLSI, CAD, timing verification, optimal clocking dblp
Rizos Sakellariou	Lecturer U of Manchester, UK cs.man.ac.uk/~rizos		parallel and distributed systems, optimising and parallelising compilers, performance modelling, software support for metacomputing and the Grid, Internet computing dblp
Mariagiovanna Sami	Professor Politecnico di Milano, Italy elet.polimi.it/internet/personai.asp?ID=sami		digital architecture design, defect and fault-tolerance of digital architectures, parallel architectures, low-power design, high-level synthesis dblp
Eduardo Sanchez	Logic Systems Laboratory, Lausanne, Switzerland lslwww.epfl.ch/pages/staff/sanchez		high complexity programmable circuits, cellular networks dblp
Alberto L. Sangiovanni-Vincentelli	Professor UC Berkeley, ECE www-cad.eecs.berkeley.edu/~alberto		design technology, computer-aided analysis and design, embedded system design dblp
Vivek Sarkar	IBM T. J. Watson research.ibm.com/people/v/vsarkar		Java, Jalapeno, array SSA, compilers dblp
Majid Sarrafzadeh	Professor Northwestern U ECE ece.northwestern.edu/~majid/		VLSI CAD, physical design, low-power design, reconfigurable computing and FPGAs, embedded systems, design and analysis of algorithms, computational complexity dblp
Toshinori Sato	Professor Kyushu Institute of Technology, Iizuka, Japan mickey.ai.kyutech.ac.jp/~tsato		microprocessor architecture and design dblp
Ashley Saulsbury	Sun		Simple COMA, memory hierarchies dblp
Yiannakis Sazeides	Professor U of Cyprus, Greece cs.ucy.ac.cy/~yanos		computer architecture, high performance microprocessors, ILP, predictability, novel execution paradigms, simultaneous multithreading dblp
Klaus E. Schauser	Professor UC Santa Barbara, CS cs.ucsb.edu/~schauser		parallel computing, Java-based global computing, SCI-based cluster computing, compilers, computer architecture dblp
Isaac D. Scherson	Professor UC Irvine ics.uci.edu/~isaac		operating systems for parallel computers, interconnection networks, performance evaluation, parallel algorithms, simulation models dblp
Michael S. Schlansker	Hewlett-Packard trimaran.org/car_group/mike_schlansker.html		EPIC, embedded systems dblp
Herman Schmit	Professor Carnegie Mellon U, ECE ece.cmu.edu/~herman (old)		reconfigurable hardware, PipeRench dblp
Yannis Schoinas	Intel cs.wisc.edu/~schoinas/schoinas.html (old)		parallel systems, system area networks, operating systems, computer systems architecture dblp
Robert Schreiber	Project scientist Hewlett-Packard Labs trimaran.org/car_group/rob_schreiber.html		Trimaran, Elcor, matrix algorithms, MATLAB, HPF dblp
Michael Schulte	Professor Lehigh U eecs.lehigh.edu/~mschulte		hardware and software for numerical computations, architectures and compilers for DSP, application-specific processor design, architectures and compilers for interval arithmetic dblp
Martin Schulz	Postdoc Cornell U, ECE csl.cornell.edu/~schulz		parallel languages and tools, SCI-based multiprocessor systems and clusters, hybrid software and hardware DSM systems, shared memory programming models, monitoring and tool support for shared memory programming, distributed and parallel I/O for clusters dblp
Assaf Schuster	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~assaf		parallel and distributed computing, peer-to-peer computing, large-scale data mining, scalable model checking, high-performance computer architecture, shared memory consistency models, Java memory model, distributed shared memory, fault tolerance, non-stop systems dblp
Michael I. Schwartzbach	Professor U of Aarhus, Denmark brics.dk/~mis		programming language design/implementation/analysis, monadic second-order logic, web technology dblp
Dana S. Scott	Professor (emeritus) Carnegie Mellon U, CS cs.cmu.edu/~scott Turing (1976) award		logic, type theory, philosophy, non-deterministic finite-state machines, realizability, domain theory dblp
Michael L. Scott	Professor U of Rochester, CS cs.rochester.edu/u/scott		parallel and distributed systems software, multiprocessor synchronization and memory coherence, operating systems, program development tools, compiler technology, programming language design dblp
Steve Scott	Cray Inc Maurice Wilkes (2005) award		interconnection networks, synchronization, multiprocessor cache coherence dblp
Carl-Johan H. Seger	Intel Strategic CAD Labs intel.com/research/scl/people/seger_c.htm		hardware verification, asynchronous circuits dblp
Peter-Michael Seidel	Professor Southern Methodist U seas.smu.edu/~seidel		computer arithmetic dblp
Luc Séméria	R&D Engineer Synopsis Inc. chronos.stanford.edu/users/lucs		hardware synthesis from C/C++ dblp
Ravi Sethi	President Avaya Labs cm.bell-labs.com/who/ravi (old)		compilers dblp
Julian Seward	ukuug.org/bios+profiles/JSeward.shtml		Glascow Haskell Compiler, valgrind, bzip dblp
André Seznec	Research director IRISA/INRIA, France irisa.fr/caps/people/seznec/index_en.htm		cache architecture, processor organisation, sequencing and branch prediction, simultaneous multithreading, SALTO, Calvin2+DICE, truly random number generation dblp
Edwin Sha	Professor U of Texas at Dallas utdallas.edu/~edsha		parallel processing, parallel architectures, high-level synthesis in VLSI, fault-tolerant computing, CAD for application-specific systems, VLSI architectures, software tools for parallel and distributed systems dblp
Hazim Shafi	IBM Research www-ece.rice.edu/~shafi		computer architecture, parallel and distributed computation dblp
Naresh R. Shanbhag	Professor U of Illinois at Urbana-Champaign, ECE cims.csl.uiuc.edu/~shanbhag/myhome		communication systems and IC design, noise-tolerant VLSI, bounds on energy and throughput efficiency of integrated microsystems dblp
Mark Shand	Hewlett-Packard System Research Center research.compaq.com/SRC/personal/shand/home.html		reconfigurable computing, PCI Pamette dblp
Natarajan Shankar	SRI International csl.sri.com/users/shankar/shankar.html		linear logic and proof theory, formal methods program, PVS dblp
Priti Shankar	Professor Indian Institute of Science, Bangalore, India drona.csa.iisc.ernet.in/~priti		compiler tools, coding theory, automata theory and formal languages dblp
Claude E. Shannon	(deceased) Bell Labs, Lucent/MIT web.mit.edu/newsoffice/tt/2001/feb28/obitshannon.html National Medal of Science		information theory, coding theory, cryptography dblp
John Paul Shen	Director, Microarchitecture Research Intel intel.com/pressroom/kits/bios/jshen.htm		microarchitecture dblp
Kenneth L. Shepard	Professor Columbia U, CS cisl.columbia.edu/faculty/shepard		design tools for advanced CMOS, SOI circuits, on-chip test and measurement circuitry, low-power design for DSP, CMOS gene chips dblp
Timothy Sherwood	Professor UC Santa Barbara CS cs.ucsb.edu/~sherwood		computer architecture, embedded systems, program phase behavior, SimPoint dblp
Olin Shivers	Professor Georgia Tech U, CS cc.gatech.edu/~shivers		advanced programming languages, systems, personal user interfaces, Scheme dblp
Sandeep K. Shukla	Professor Virginia Tech, ECE filebox.vt.edu/users/shukla		formal methods, system level power management, system level design and verification, ad-hoc networks dblp
Howard Jay Siegel	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~hj		parallel processing, heterogeneous computing, computer architecture, interconnection networks, parallel algorithms dblp
Daniel P. Siewiorek	Director of Human Computer-Interaction Institute Carnegie Mellon U cs.cmu.edu/~dps Eckert-Mauchly (1988) award		wearable computers, fault tolerance, CM* dblp
Gabriel M. Silberman	IBM Software Solutions Divisions, Toronto, Canada cas.ibm.com/director		computer architecture, compilers, digital circuit testing dblp
Jurij Silc	Researcher Jozef Stefan Institute, Ljubljana, Slovenia anica.ijs.si/silc		processor architecture, multithreaded computing, high-level synthesis, parallel processing, evolution algorithms dblp
Elizabeth A. Simon	Professor U of San Diego CS sandiego.edu/~bsimon		compilers, computer architecture, performance programming, scientific computing, EPIC compilation dblp
Tajana Simunic	Hewlett-Packard Labs akebono.stanford.edu/users/tajana/		system-level hardware and software design, wireless, embedded and low-power systems dblp
Jaswinder Pal Singh	Professor Princeton U, CS cs.princeton.edu/~jps		parallel architectures dblp
Montek Singh	Professor U of North Carolina CS cs.unc.edu/~montek		high-performance and low-power digital design, VLSI CAD, asynchronous circuits dblp
Satnam Singh	Microsoft Research xilinx.com/labs/satnam (old)		hardware description languages, formal verification for core verification, reconfigurable computing, layout analysis dblp
Henk J. Sips	Professor Delft U, Netherlands pds.twi.tudelft.nl/~henk		parallel algorithms, parallel computer architecture, parallel programming languages dblp
Mukund Sivaraman	R&D engineer Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/mukund-sivaraman-page.html		timing and functional verification for ASIC, PICO dblp
Anand Sivasubramaniam	Professor Penn State U cse.psu.edu/~anand		computer architecture, operating systems, parallel computing, simulation and evaluation of dblp
Kevin Skadron	Professor U of Virginia, CS cs.virginia.edu/~skadron		HydraScalar, multipath execution dblp
Alexander Skavantzos	Professor Louisiana State U ece.lsu.edu/alex		computer arithmetic, computer architecture, ASIC design, VLSI signal processing, parallel processing dblp
Jonas Skeppstedt	Professor Lunds U, Sweden cs.lth.se/~js		compiler controlled data prefetching dblp
Konrad Slind	Professor U of Utah, CS cs.utah.edu/~slind		higher order logic, formal verification dblp
Yannis Smaragdakis	Professor Georgia Tech U, CS cc.gatech.edu/~yannis		object-oriented language design, tools to facilitate program construction, memory management dblp
Alan J. Smith	Professor UC Berkeley, CS cs.berkeley.edu/People/Faculty/Homepages/smith.html		caches, power management dblp
Burton J. Smith	Chief scientist Cray Inc Eckert-Mauchly (1991) award		high-performance computer architecture, parallel programming languages, MTA dblp
James E. Smith	Professor U of Wisconsin-Madison, ECE engr.wisc.edu/ece/faculty/smith_james.html Eckert-Mauchly (1999) award		Trace cache, Trace processor, Multiscalar dblp
Michael D. Smith	Professor Harvard U eecs.harvard.edu/~smith		Machsuif, compiler back-end dblp
Mark Smotherman	Professor Clemson U cs.clemson.edu/~mark		reliability, performance modeling, computer architecture dblp
Greg Snider	Hewlett-Packard Labs trimaran.org/car_group/greg_snider.html (old)		Elcor, compilation for reconfigurable hardware, PICO dblp
Marc Snir	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~snir		IBM Blue Gene, NYU Ultracomputer, MPI, IBM SP scalable parallel system, parallel algorithms, parallel architectures, interconnection networks, parallel programming environments dblp
Avinash Sodani	Intel, Hillsboro cs.wisc.edu/~sodani/sodani.html (old)		dynamic instruction reuse dblp
Mary Lou Soffa	Professor U of Virginia, CS cs.virginia.edu/~soffa		continuous and adaptive compilation, path and resource sensitive optimizations, experimental evaluation of optimizations, debugging optimized code, demand driven data flow, GUI testing dblp
Gurindar S. Sohi	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~sohi Maurice Wilkes (1999) award		Multiscalar, speculative execution dblp
Yan Solihin	Professor North Carolina State U cesr.ncsu.edu/solihin		memory hierarchy organization, asymmetric architecture, customizable threads, processor-memory integration, self-optimizing systems dblp
Arun K. Somani	Professor Iowa State U, EE vulcan.ee.iastate.edu/~arun		fault tolerant computing, computer interconnection networks, optical networking, computer architecture, parallel computer systems dblp
Fabio Somenzi	Professor U of Colorado at Boulder, ECE vlsi.colorado.edu/~fabio		formal verification, CUDD, VIS, CAD, logic minimization dblp
Daniel J. Sorin	Professor Duke U, EE ee.duke.edu/~sorin		SMP, high availability servers, memory system design, verification of memory consistency, performance analysis dblp
Christos P. Sotiriou	Professor ICS-FORTH, Heraklion, Crete, Greece ics.forth.gr/~sotiriou		asynchronous circuit design and testing, industrial EDA tools for asynchronous design dblp
Jens Sparsø	Professor Technical U of Denmark imm.dtu.dk/~jsp		architecture and design of VLSI systems, asynchronous logic dblp
Evan Speight	Professor Cornell U, ECE csl.cornell.edu/~espeight		distributed computing, parallel processing, computer architecture, location-independent data access, operating systems dblp
Ellen Spertus	Professor Mills College mills.edu/ACAD_INFO/mcs_spertus.html		information retrieval, Internet, social issues, computer architecture, compilers dblp
Amitabh Srivastava	Vice President Microsoft research.microsoft.com/users/amitabhs		ATOM, programmer productivity, software engineering dblp
Richard M. Stallman	President Free Software Foundation stallman.org		Emacs, gcc, bison dblp
Mircea Stan	Professor U of Virginia, EE ee.virginia.edu/~mrs8n		low-power encoding methods and circuits, CAD for high-level power estimation, circuit design for novel low-power devices, low-power system integration dblp
Bjarne Steensgaard	Researcher Microsoft Research research.microsoft.com/~rusa		alias analysis, VDG, Java, C dblp
Darko Stefanovic	Professor U of New Mexico CS cs.unm.edu/~darko		dynamic cooperative performance optimization for Java, dynamic binary translation, computing with biochemical molecules dblp
J. Gregory Steffan	Professor U of Toronto, EE, Canada eecg.toronto.edu/~steffan		thread-level data speculation dblp
Bernhard Steffen	Professor U of Dortmund, Germany ls5-www.cs.uni-dortmund.de/staff/steffen.en.html		static analysis, lazy code motion, formal verification dblp
Per Stenström	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~pers		high-performance computers, multiprocessors for multimedia/database/numeric applications dblp
Thomas L. Sterling	Professor Caltech U cacr.caltech.edu/~tron		Beowulf, Hybrid Technology Multithreaded Architecture (HTMT), parallel computer architecture, system software, evaluation dblp
James E. Stine	Professor Illinois Institute of Technology, ECE ece.iit.edu/~jstine		computer arithmetic, computer architecture, VLSI, CAD techniques, reliable computing, compilers, digital circuit design, FPGA and DSP architectures dblp
Paul Stodghill	Research Associate Cornell U, CS cs.cornell.edu/stodghil		sparse compilation, sparse computations, fault-tolerance and dynamic resource management for scientific computations, extensible and open compiler systems, programming systems for HPC dblp
Mark G. Stoodley	U of Toronto, Canada eecg.toronto.edu/~stoodla		low-level compiler optimizations and related architectural features, vector microprocessors dblp
Quentin F. Stout	Professor U of Michigan eecs.umich.edu/~qstout		parallel and scientific computing, adaptive sampling designs, algorithms and data structures, operator theory and analysis dblp
Andrzej J. Strojwas	Professor Carnegie Mellon U, ECE ece.cmu.edu/people/show.php?type=faculty&id=171		design and manufacturing of ULSIC dblp
Bjarne Stroustrup	AT&T Research/Texas A&M U research.att.com/~bs/homepage.html ACM Grace Murray Hopper award (1983) award		C++ dblp
Volker Strumpen	Research scientist MIT cag.lcs.mit.edu/~strumpen		Porch: portable checkpoint compiler, Cilk, distributed operating systems, RAW operating system dblp
Michael Stumm	Professor U of Toronto, Canada eecg.utoronto.ca/~stumm		operating systems for distributed and parallel systems, multiprocessor architectures, DSM, parallel file systems, parallel compilers, Hector Multiprocessor, Hurricane OS, NUMAchine multiprocessor, Tornado OS dblp
Zhendong Su	Professor UC Davis, CS cs.ucdavis.edu/~su		static analyses for error detection dblp
Bronis R. de Supinski	Lawrence Livermore National Lab llnl.gov/CASC/people/de_supinski		cache coherence and distributed shared memory, consistency semantics, networks of workstations, distributed object computing, parallel and distributed simulation dblp
Ivan E. Sutherland	Sun sun.com/960710/feature3/ivan-profile.html Turing (1988) award, von Neumann medal, computer graphics award		asynchronous logic, micropipelines, Counterflow dblp
Bertil P. Svensson	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/People/svensson.html		parallel processing for embedded systems, distributed massively parallel architectures, neurocomputers, real-time systems dblp
Philip H. Sweany	Texas Instruments		compilation for VLIW dblp
Peter F. Sweeney	IBM Research T. J. Watson research.ibm.com/people/p/pfs/		analysis and optimization of object-oriented languages, software distribution dblp
Dennis Sylvester	Professor U of Michigan eecs.umich.edu/~dennis		modeling/characterization/analysis of deep submicron device technology dblp
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Mehdi Baradaran Tahoori	Professor Northeastern U ece.neu.edu/faculty/mtahoori		FPGA Testing, VLSI Test Automation, reliability and fault tolerance, test, defect and fault tolerance for molecular and nano-technology, noise issues in deep sub-micron VLSI, CAD, reconfigurable computing dblp
Deependra Talla	System Architect Texas Instruments ece.villanova.edu/~deepu		computer architecture, multimedia and DSP, workload characterization, ASIC and FPGA design dblp
Madhusudhan Talluri	Sunsoft, Sun cs.wisc.edu/~talluri/talluri.html (old)		virtual memory dblp
Andrew S. Tanenbaum	Professor Vrije U., Amsterdam, Netherlands cs.vu.nl/~ast/		distributed systems, compilers, many textbooks dblp
Zhimin Tang	Professor Institute of Computing Technology, Chinese Academy of Sciences ict.ac.cn/chpc/tang		ASIC design, parallel processing, dblp
Olivier Tardieu	Postdoc Columbia U CS www1.cs.columbia.edu/~tardieu		alias analysis, embedded systems dblp
Robert Endre Tarjan	Professor Princeton U, CS cs.princeton.edu/~ret Turing (1986) award		graph algorithms dblp
Valerie E. Taylor	Professor Texas A&M U, CS cs.tamu.edu/people/faculty/taylor		high performance computing, performance analysis and modeling of parallel and distributed applications dblp
Jürgen Teich	Professor U Erlangen-Nuremberg, Germany www12.informatik.uni-erlangen.de/people/teich/index.php		embedded systems, scheduling theory and optimization, massively parallel VLSI architectures dblp
Tim Teitelbaum	Professor Cornell U cs.cornell.edu/Info/People/tt/Tim_Teitelbaum.html		incremental computation, transformational programming, programming environments, language-based editors, compilers, attribute grammars, Ada, synthesizer dblp
Olivier Temam	Professor U Paris Sud, France lri.fr/~temam		microarchitecture, memory locality dblp
Dan Teodosiu	Researcher Microsoft Research		multiprocessors, Scheme, compression dblp
Russell Tessier	Professor U Massachusetts Amherst ecs.umass.edu/ece/tessier		hardware verification, reconfigurable hardware, CAD and logic synthesis dblp
Charles P. Thacker	Microsoft Research Silicon Valley nae.edu/NAE/awardscom.nsf/weblinks/LRAO-5X4TYX?OpenDocument		Firefly, Xerox Alto, Tablet PC, Ethernet, AUTONET dblp
Chandramohan A. Thekkath	Microsoft Research research.microsoft.com/~thekkath		operating systems, distributed systems, networks, interaction architecture/OS dblp
Kevin B. Theobald	Professor U of Delaware capsl.udel.edu/~theobald		multithreaded architectures, branch prediction, EARTH dblp
Michael Theobald	Postdoc Carnegie Mellon U CS www-2.cs.cmu.edu/~theobald		asynchronous circuits, formal verification, CAD, logic and high-level synthesis, BDD and SAT Techniques, embedded and hybrid systems dblp
Lothar Thiele	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~thiele		models/methods/software tools for embedded systems design, array processors, parallel algorithms for signal and image processing, combinatorial optimization, cryptography dblp
Donald E. Thomas	Professor Carnegie Mellon U, ECE ece.cmu.edu/~thomas		hardware/software co-design, Verilog dblp
Carol L. Thompson	Hewlett-Packard		compilers for Itanium dblp
Ken Thompson	Bell Labs, Lucent cm.bell-labs.com/cm/cs/who/ken (old) Turing (1983) award		Unix, Plan 9 dblp
Mithuna S. Thottethodi	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~mithuna		microarchitecture, communication in distributed microarchitectures, systems architecture, interconnection networks dblp
Michael D. Tiemann	Vice President RedHat Inc. redhat.com/about/corporate/team/tiemann.html		g++, Cygnus dblp
Frank Tip	IBM T.J. Watson research.ibm.com/people/t/tip		whole-program optimization of object-oriented applications, program analyis/slicing/understanding/refactoring, compiler optimization dblp
Francisco Tirado	Professor U Complutense de Madrid, Spain dacya.ucm.es/paco		parallel processing for scientific computing, scalability of parallel systems, parallel architectures, processor microarchitecture dblp
Robert Tomasulo	IBM ? Eckert-Mauchly (1997) award		Tomasulo's algorithm (out-of-order execution)
Hiroyuki Tomiyama	Professor Nagoya U, Japan ertl.jp/~tomiyama		system-level design methodologies for system-on-chip, high-level synthesis, compilers for low-power embedded systems, analysis and optimization of real-time software dblp
Karen A. Tomko	Professor U of Cincinatti ece.uc.edu/~ktomko		reconfigurable computing, high performance computing, scientific application performance, graph partitioning, compiler assisted optimization dblp
Linda Torczon	Research scientist Rice U, CS cs.rice.edu/~linda		code generation, interprocedural dataflow analysis, ParaScope dblp
Hwa C. Torng	Professor (emeritus) Cornell U, ECE ee.cornell.edu/people/faculty/torng/htorng.shtml		advanced RISC and superscalar architecture, design of intelligent and broadband telecommunication networks, task scheduling in multi-processors dblp
Josep Torrellas	Professor U of Illinois Urbana-Champaign, CS iacoma.cs.uiuc.edu/~torrella		Polaris, I-ACOMA, FlexRAM dblp
Nur A. Touba	Professor U of Texas, Austin, ECE ece.utexas.edu/~touba		CAD, testing, fault tolerant computing dblp
Dan Truong	Hewlett-Packard irisa.fr/caps/people/truong (old)		software cache optimization, data and instruction layout and prefetching, profile-based optimization dblp
Dean M. Tullsen	Professor UC San Diego www-cse.ucsd.edu/users/tullsen		SMT, speculation, ILP dblp
Gary Scott Tyson	Professor U of Michigan eecs.umich.edu/~tyson		computer architecture, compiler optimization dblp
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Gang-Ryung Uh	Professor Boise State U cs.boisestate.edu/~uh		embedded processors software tools dblp
Augustus K. Uht	Professor U of Rhode-Island ele.uri.edu/~uht		ILP, timing analysis dblp
Jeffrey D. Ullman	Professor Stanford U www-db.stanford.edu/~ullman		compilers, databases dblp
Stephen H. Unger	Professor Columbia U, CS cs.columbia.edu/~unger		self-timed systems dblp
Theo Ungerer	Professor U of Augsburg, Germany informatik.uni-augsburg.de/~ungerer/welcome-eng.html		processor architecture, embedded real-time systems, ubiquitous systems dblp
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Frank Vahid	Professor UC Riverside, CS cs.ucr.edu/~vahid		embedded systems design dblp
Ramachandran Vaidyanathan	Professor Louisiana State U ECE ece.lsu.edu/vaidy		parallel algorithms and models, optical interconnects, dynamic reconfiguration, bus-based architectures dblp
Sriram Vajapeyam	consultant cs.wisc.edu/~sriram (old)		instruction issue, trace processors, superscalar processor design, run-time program vectorization dblp
Mateo Valero	Professor U Politecnica de Catalunya, Barcelona, Spain people.ac.upc.es/mateo		microarchitecture, compilers dblp
Murali R. Varanasi	Professor U of South Florida csee.usf.edu/faculty/varanasi.htm		coding theory, computer arithmetic, fault tolerant computing, VLSI design dblp
Stamatis Vassiliadis	Professor Technical U of Delft, Netherlands einstein.et.tudelft.nl/~stamatis		parallel embedded systems, computer architecture, hardware design, custom computing machines, computer arithmetic, low power design, Internet processing dblp
Jack Veenstra	Silicon Graphics cs.rochester.edu/u/veenstra (old)		MINT simulator dblp
Alexander V. Veidenbaum	Professor UC Irvine cecs.uci.edu/~alexv		computer Architecture, compilers, embedded Systems dblp
Helmut Veith	Professor U of Vienna, Austria dbai.tuwien.ac.at/staff/veith		formal verification, model checking, temporal logic, security dblp
Andreas G. Veneris	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~veneris/AndreasVeneris.htm		CAD tools for synthesis/optimization/testing, algorithms and theory dblp
Mary K. Vernon	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~vernon		performance modeling dblp
Narayanan Vijaykrishnan	Professor Penn State U cse.psu.edu/~vijay		low power VLSI, Java computing, computer architecture, embedded systems dblp
T. N. Vijaykumar	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~vijay		ILP, Multiscalar, gated-Vdd dblp
Lucian N. Vintan	Professor Lucian Blaga U of Sibiu, Romania webspace.ulbsibiu.ro/lucian.vintan/		branch prediction, value prediction, prediction techniques for ubiquitous computing dblp
Kees A. Vissers	Trimedia, Netherlands ptolemy.eecs.berkeley.edu/~vissers (old)		media processors, digital signal processing, hardware-software co-design dblp
Jan Vitek	Professor Purdue U, CS cs.purdue.edu/homes/jv/index.html		semantics and implementation of programming languages, semantics-based software engineering tools, secure software systems, customizable virtual machines, aliasing and ownership, real-time Java, cluster virtual machines, transactional programming languages dblp
Michael J. Voss	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~voss		tools and compilers for parallel computing dblp
Zvonko G. Vranesic	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~zvonko		multiprocessor systems, VLSI systems and local area networks, NUMAchine dblp
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Philip Wadler	Researcher Avaya Labs research.avayalabs.com/user/wadler		XML, Java, functional languages, Haskell, Erlang, logic and programming dblp
Robert Wagner	Professor Duke U, CS cs.duke.edu/~raw		loop scheduling dblp
Larry Wall	wall.org/~larry		Perl, patch, rn dblp
Hong Wang	Researcher Santa Clara Intel Microarchitecture Lab intel.com/research/mrl/people/wang_h.htm		performance modelling, IA-64 dblp
Jun Wang	Professor U of Nebraska, Lincoln cse.unl.edu/~wang		high performance I/O architectures and storage systems, file systems, peer-to-peer systems, cluster and grid computing, internet server and technology, performance evaluation dblp
Wen-Hann Wang	manager of Emerging Platforms Lab Intel, Hillsboro		caches, computer architecture dblp
Nancy J. Warter-Perez	Professor California State U at Los Angeles calstatela.edu/faculty/nwarter/nwareter.htm		computer architecture, high-performance processor design, compiler design, instruction scheduling, EPIC processors dblp
John Wawrzynek	Professor UC Berkeley, CS cs.berkeley.edu/~johnw		BRASS, GARP dblp
Charles C. Weems	Professor U of Massachusetts, Amherst, CS cs.umass.edu/~weems		associative processing and architectures, parallel architectures for image processing, heterogeneous parallel architectures and compilers, integration of compile-time and run-time information dblp
Mark N. Wegman	IBM research.ibm.com/people/w/wegman		SSA, program optimization, programming languages dblp
William E. Weihl	CTO Akamai akamai.com/en/html/about/management_bw.html		DCPI, distributed and parallel computing, transaction processing, parallel programming languages, distributed garbage collection, replication, scheduling dblp
Markus Weinhardt	Researcher PACT, Germany markus-weinhardt.de		reconfigurable hardware compilation dblp
Stephanie Weirich	Professor U of Pennsylvania, CS cis.upenn.edu/~sweirich		programming languages, type theory, functional programming, logic, language-based security dblp
Daniel Weise	Microsoft Research research.microsoft.com/~daniel		program slicing, programming languages, VDG dblp
Uri C. Weiser	Director of Streaming Technology, Corporate Technology Group Intel intel.com/pressroom/kits/bios/uweiser.htm		Pentium, MMX dblp
David B. Whalley	Professor Florida State U cs.fsu.edu/~whalley		optimizing compilers, computer architecture, performance evaluation, real-time systems dblp
Reinhard Wilhelm	Professor U des Saarlandes, Saarbrucken, Germany rw4.cs.uni-sb.de/~wilhelm		static program analysis, embedded systems, security, animation and visualisation dblp
Maurice V. Wilkes	Advisor on research policy AT&T Research xorl.org/people/mvw Turing (1967) award, Eckert-Mauchly (1980) award		EDSAC, stored-program computers, microprogramming, caches, distributed memories dblp
Linda M. Wills	Professor Georgia Tech, ECE users.ece.gatech.edu/~linda		software understanding and retargeting, parallelization of portable multimedia applications, rapid prototyping of reconfigurable embedded software, binary reverse engineering dblp
Scott Wills	Professor Georgia Tech U, ECE users.ece.gatech.edu/~scotty		focal plane architectures, short wire architectures, VLSI and GSI semiconductor technology, portable multimedia supercomputers, image processing architectures dblp
Steve J. E. Wilton	Professor U of British Columbia, Canada ece.ubc.ca/~stevew		computer architecture, VLSI design dblp
Jeannette M. Wing	Professor Carnegie Mellon U, CS cs.cmu.edu/~wing		Software specification and verification, security, concurrent and distributed systems, programming languages, programming methodology dblp
Niklaus Wirth	Professor emeritus ETH Zurich cs.inf.ethz.ch/~wirth Turing (1984) award		Pascal, Modula-2, Oberon, CAD Tools for Hardware Design (Lola) dblp
Michael J. Wirthlin	Professor Brigham Young U, EE ee.byu.edu/faculty/wirthlin		reconfigurable hardware, JHDL dblp
Emmett Witchel	Professor U of Texas Austin CS cs.utexas.edu/users/witche		network processors, Mondriaan memory protection, machine learning for scheduling dblp
Mario Wolczko	Senior staff engineer Sun Research research.sun.com/people/mario		architectural support for object-oriented languages, Mushroom dblp
Tilman Wolf	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/wolf		network processors, programmable routers dblp
Wayne Wolf	Professor Princeton U, EE ee.princeton.edu/~wolf		embedded computing systems, video architectures, multimedia information systems dblp
Andrew Wolfe	Senior Vice President and CTO SonicBlue sonicblue.com/default.asp?menu=Company&sub_menu=Key_Management&item=Andy_Wolfe		3D graphic accelerators dblp
Michael R. Wolfe	ST Microelectronics		parallelizing compilers, vectorization dblp
Martin D. F. Wong	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?mdfwong		CAD, field-programmable systems, design and analysis of algorithms, combinatorial optimization dblp
David A. Wood	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~david		computer architecture, parallel computing, memory systems, performance evaluation dblp
Jim Woodcock	Reader Oxford U, UK web.comlab.ox.ac.uk/oucl/work/jim.woodcock		software engineering, formal methods, mechanised proofs, security and safety, Z dblp
Jie Wu	Professor Florida Atlantic U cse.fau.edu/~jie		wireless networks and mobile computing, parallel and distributed systems, fault tolerant computing, load balancing in multicomputers, software engineering dblp
Youfeng Wu	Intel MRL intel.com/research/mrl/people/wu_y.htm		advanced compiler transformations, profile-guided optimizations, instruction-level parallelism, performance analysis with large workloads dblp
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Yuan Xie	Professor Penn State U. cse.psu.edu/~yuanxie		VLSI design, computer architecture, embedded systems design, electronics design automation (EDA) dblp
Jingling Xue	Professor University of New South Wales, Australia cse.unsw.edu.au/~jxue		compiler optimisations, instruction-level parallelism, parallelising compilers, memory hierarchies, compilers for embedded systems dblp
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Alex Yakovlev	Professor University of Newcastle, UK staff.ncl.ac.uk/alex.yakovlev		asynchronous vlsi, Petri Nets and concurrency models, Hardware Description Languages, CAD for VLSI, fault tolerance and reliability in VLSI, Petrify dblp
Qing (Ken) Yang	Professor U of Rhode-Island ele.uri.edu/~qyang		distributed web server architectures, disk I/O systems, e-commerce dblp
Yuanyuan Yang	Professor State U of New York at Stony Brook, ECE nrl0.ece.sunysb.edu/~yang		parallel and distributed computing, high speed networks, optical networks, high performance computer architecture, fault-tolerant computing dblp
Svetlana N. Yanushkevich	Professor U of Calgary, Canada enel.ucalgary.ca/People/yanush		CAD, multiple-valued logic, decision diagrams, nanoarchitectronics dblp
Hiroto Yasuura	Professor Kyushu U, Japan kasuga.csce.kyushu-u.ac.jp/~yasuura		hardware/software co-design, design methodologies for systems-on-a-chip, embedded system design, information technology for social infrastructure, low power and low energy system design dblp
Katherine Yelick	Professor UC Berkeley, CS cs.berkeley.edu/~yelick		parallel computing, memory hierarchy optimizations, programming languages, compilers dblp
Daniel M. Yellin	director IBM Research Software Technology Department		distributed computing, program analysis, algorithms for incremental computation dblp
Donald Yeung	Professor U of Maryland, ECE ece.umd.edu/~yeung		Vortex, Multigrain systems, MIT Alewife dblp
Pen-Chung Yew	Professor U of Minesotta www-users.cs.umn.edu/~yew		high-performance microprocessor architectures, parallelizing compilers, parallel machine organizations, performance evaluation, parallel discrete event-driven simulations dblp
Adi Yoaz	Computer Architect Intel Texas Development Center home.austin.rr.com/yoaz		high performance computing systems, cache architectures, branch prediction, memory disambiguation, data prefetching, speculative execution, ILP dblp
Honesty C. Young	IBM Research, Almaden		computer architecture for databases, disk systems dblp
Ki Hwan Yum	Professor U of Texas at San Antonio cs.utsa.edu/~yum		computer architecture, parallel and distributed systems, computer networks, cluster computing, QoS Support in cluster networks and Internet, performance evaluation, fault-tolerant computing, power efficient systems, embedded systems dblp
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F. Kenneth Zadeck	Founder, Chief Technology Officer NaturalBridge		program analysis, SSA, optimizing compilers dblp
Mohamed M. Zahran	Professor City U of New York mzahran.com		microarchitecture of multithreaded processors, power-aware architecture, high performance memory hierarchy dblp
Safwat G. Zaky	Professor U of Toronto, EE, Canada eecg.utoronto.ca/~safwat		computer architecture and hardware, digital circuit design, computer communication, digital switching and LANs, environmental awareness dblp
Andreas Zeller	Professor U des Saarlandes, Germany st.cs.uni-sb.de/~zeller/		automated debugging, self-healing programs, software evolution, experimental program analysis, exploit generation dblp
Antonia Zhai	Professor U of Minnesota www2.itdean.umn.edu/faculty/detail.jsp?facultyID=503		compiler optimizations, computer architecture dblp
Lintao Zhang	Microsoft Research research.microsoft.com/users/lintaoz		formal verification, SAT solvers, Chaff dblp
Wei Zhang	Professor Southern Illinois U, Carbondale ECE howard.engr.siu.edu/~zhang/		computer architecture, compilers, hardware/software co-design for embedded systems dblp
Xiaodong Zhang	Professor College of William and Mary, CS cs.wm.edu/~zhang		memory performance improvement, memory-centric resource management, cluster computing dblp
Youtao Zhang	Professor U of Texas Dallas utdallas.edu/~yxz028100		secure systems, program analysis, profiling and code optimization, computer architecture, embedded systems dblp
Zhao Zhang	Professor Iowa State U ECE clue.eng.iastate.edu/~zzhang		high performance computer architecture, parallel and distributed computing, architectural support for security dblp
Xudong Zhao	staff engineer Strategic CAD Labs, Intel		formal verification for hardware and arithmetic circuits dblp
Peixin Zhong	Professor Michigan State U ECE egr.msu.edu/~pzhong		VLSI, computer architecture, adaptable system-on-chip dblp
Dian Zhou	Professor U of Texas at Dallas utdallas.edu/~zhoud		VLSI, CAD tools, circuits and systems dblp
Hai Zhou	Professor Northwestern U ECE ece.northwestern.edu/~haizhou		VLSI CAD, algorithm design, formal methods dblp
Huiyang Zhou	Professor U of Central Florida CS cs.ucf.edu/~zhou/		computer architecture, high-performance/low-power/DSP, back-end compiler design, code optimization, embedded systems dblp
Yuanyuan Zhou	Professor U of Illinois at Urbana-Champaign CS www-faculty.cs.uiuc.edu/~yyzhou		operating systems, file and storage systems, computer architecture, distributed systems, parallel systems, system support for databases dblp
Jianwen Zhu	Professor U of Toronto, EE, Canada eecg.toronto.edu/~jzhu		computer aided design for digital IC, synthesis, OpenJ dblp
Sotirios G. Ziavras	Professor New Jersey Institute of Technology megahertz.njit.edu/~ziavras		computer architecture, parallel processing and supercomputing dblp
Craig B. Zilles	Professor U of Illinois at Urbana-Champaign, CS www-faculty.cs.uiuc.edu/~zilles		dynamic program slicing, prediction dblp
Hans P. Zima	Professor U of Vienna, Austria par.univie.ac.at/~zima		parallel computation, HPF+, object-based distributed programming for massively parallel arrays of processor-in-memory systems dblp
Wolf Zimmermann	Professor Martin-Luther U Halle-Wittenberg, Germany informatik.uni-halle.de/~zimmer		reliable compilers, software engineering, programming languages dblp
Benjamin G. Zorn	Microsoft Research research.microsoft.com/~zorn		hybrid value predictors, garbage collection, programming languages, runtime environments dblp
Konrad Zuse	(deceased) konrad-zuse.de		first program-controlled digital computer dblp
Willy Zwaenepoel	Professor Rice U, CS cs.rice.edu/~willy		DSM, Munin, Threadmarks, ScalaServer, Puppeteer dblp
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