Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Shmuel Sagiv	Professor Tel Aviv U, Israel math.tau.ac.il/~msagiv		programming languages, compilers, abstract interpretation, profiling, pointer analysis, interprocedural dataflow analysis, program slicing, porting source code, language-based programming environments dblp
Sartaj K. Sahni	Professor U of Florida cise.ufl.edu/~sahni		data structures and algorithms, scheduling, optimization, VLSI CAD, computational geometry, image processing, medical applications dblp
Pascal Sainrat	U Paul Sabatier, Toulouse, France irit.fr/recherches/ARCHI/MARCH/SAINRAT/ANGLAIS/sainrat.frame.shtm		interconnection networks, superscalar architectures dblp
Suleyman Sair	Professor North Carolina State U ECE cesr.ncsu.edu/ssair		computer architecture, phase-based program analysis and optimizations, adaptive scheduling for VLIW, memory hierarchy design and prefetching dblp
Karem A. Sakallah	Professor U of Michigan eecs.umich.edu/~karem		VLSI, CAD, timing verification, optimal clocking dblp
Rizos Sakellariou	Lecturer U of Manchester, UK cs.man.ac.uk/~rizos		parallel and distributed systems, optimising and parallelising compilers, performance modelling, software support for metacomputing and the Grid, Internet computing dblp
Mariagiovanna Sami	Professor Politecnico di Milano, Italy elet.polimi.it/internet/personai.asp?ID=sami		digital architecture design, defect and fault-tolerance of digital architectures, parallel architectures, low-power design, high-level synthesis dblp
Eduardo Sanchez	Logic Systems Laboratory, Lausanne, Switzerland lslwww.epfl.ch/pages/staff/sanchez		high complexity programmable circuits, cellular networks dblp
Alberto L. Sangiovanni-Vincentelli	Professor UC Berkeley, ECE www-cad.eecs.berkeley.edu/~alberto		design technology, computer-aided analysis and design, embedded system design dblp
Vivek Sarkar	IBM T. J. Watson research.ibm.com/people/v/vsarkar		Java, Jalapeno, array SSA, compilers dblp
Majid Sarrafzadeh	Professor Northwestern U ECE ece.northwestern.edu/~majid/		VLSI CAD, physical design, low-power design, reconfigurable computing and FPGAs, embedded systems, design and analysis of algorithms, computational complexity dblp
Toshinori Sato	Professor Kyushu Institute of Technology, Iizuka, Japan mickey.ai.kyutech.ac.jp/~tsato		microprocessor architecture and design dblp
Ashley Saulsbury	Sun		Simple COMA, memory hierarchies dblp
Yiannakis Sazeides	Professor U of Cyprus, Greece cs.ucy.ac.cy/~yanos		computer architecture, high performance microprocessors, ILP, predictability, novel execution paradigms, simultaneous multithreading dblp
Klaus E. Schauser	Professor UC Santa Barbara, CS cs.ucsb.edu/~schauser		parallel computing, Java-based global computing, SCI-based cluster computing, compilers, computer architecture dblp
Isaac D. Scherson	Professor UC Irvine ics.uci.edu/~isaac		operating systems for parallel computers, interconnection networks, performance evaluation, parallel algorithms, simulation models dblp
Michael S. Schlansker	Hewlett-Packard trimaran.org/car_group/mike_schlansker.html		EPIC, embedded systems dblp
Herman Schmit	Professor Carnegie Mellon U, ECE ece.cmu.edu/~herman (old)		reconfigurable hardware, PipeRench dblp
Yannis Schoinas	Intel cs.wisc.edu/~schoinas/schoinas.html (old)		parallel systems, system area networks, operating systems, computer systems architecture dblp
Robert Schreiber	Project scientist Hewlett-Packard Labs trimaran.org/car_group/rob_schreiber.html		Trimaran, Elcor, matrix algorithms, MATLAB, HPF dblp
Michael Schulte	Professor Lehigh U eecs.lehigh.edu/~mschulte		hardware and software for numerical computations, architectures and compilers for DSP, application-specific processor design, architectures and compilers for interval arithmetic dblp
Martin Schulz	Postdoc Cornell U, ECE csl.cornell.edu/~schulz		parallel languages and tools, SCI-based multiprocessor systems and clusters, hybrid software and hardware DSM systems, shared memory programming models, monitoring and tool support for shared memory programming, distributed and parallel I/O for clusters dblp
Assaf Schuster	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~assaf		parallel and distributed computing, peer-to-peer computing, large-scale data mining, scalable model checking, high-performance computer architecture, shared memory consistency models, Java memory model, distributed shared memory, fault tolerance, non-stop systems dblp
Michael I. Schwartzbach	Professor U of Aarhus, Denmark brics.dk/~mis		programming language design/implementation/analysis, monadic second-order logic, web technology dblp
Dana S. Scott	Professor (emeritus) Carnegie Mellon U, CS cs.cmu.edu/~scott Turing (1976) award		logic, type theory, philosophy, non-deterministic finite-state machines, realizability, domain theory dblp
Michael L. Scott	Professor U of Rochester, CS cs.rochester.edu/u/scott		parallel and distributed systems software, multiprocessor synchronization and memory coherence, operating systems, program development tools, compiler technology, programming language design dblp
Steve Scott	Cray Inc Maurice Wilkes (2005) award		interconnection networks, synchronization, multiprocessor cache coherence dblp
Carl-Johan H. Seger	Intel Strategic CAD Labs intel.com/research/scl/people/seger_c.htm		hardware verification, asynchronous circuits dblp
Peter-Michael Seidel	Professor Southern Methodist U seas.smu.edu/~seidel		computer arithmetic dblp
Luc Séméria	R&D Engineer Synopsis Inc. chronos.stanford.edu/users/lucs		hardware synthesis from C/C++ dblp
Ravi Sethi	President Avaya Labs cm.bell-labs.com/who/ravi (old)		compilers dblp
Julian Seward	ukuug.org/bios+profiles/JSeward.shtml		Glascow Haskell Compiler, valgrind, bzip dblp
André Seznec	Research director IRISA/INRIA, France irisa.fr/caps/people/seznec/index_en.htm		cache architecture, processor organisation, sequencing and branch prediction, simultaneous multithreading, SALTO, Calvin2+DICE, truly random number generation dblp
Edwin Sha	Professor U of Texas at Dallas utdallas.edu/~edsha		parallel processing, parallel architectures, high-level synthesis in VLSI, fault-tolerant computing, CAD for application-specific systems, VLSI architectures, software tools for parallel and distributed systems dblp
Hazim Shafi	IBM Research www-ece.rice.edu/~shafi		computer architecture, parallel and distributed computation dblp
Naresh R. Shanbhag	Professor U of Illinois at Urbana-Champaign, ECE cims.csl.uiuc.edu/~shanbhag/myhome		communication systems and IC design, noise-tolerant VLSI, bounds on energy and throughput efficiency of integrated microsystems dblp
Mark Shand	Hewlett-Packard System Research Center research.compaq.com/SRC/personal/shand/home.html		reconfigurable computing, PCI Pamette dblp
Natarajan Shankar	SRI International csl.sri.com/users/shankar/shankar.html		linear logic and proof theory, formal methods program, PVS dblp
Priti Shankar	Professor Indian Institute of Science, Bangalore, India drona.csa.iisc.ernet.in/~priti		compiler tools, coding theory, automata theory and formal languages dblp
Claude E. Shannon	(deceased) Bell Labs, Lucent/MIT web.mit.edu/newsoffice/tt/2001/feb28/obitshannon.html National Medal of Science		information theory, coding theory, cryptography dblp
John Paul Shen	Director, Microarchitecture Research Intel intel.com/pressroom/kits/bios/jshen.htm		microarchitecture dblp
Kenneth L. Shepard	Professor Columbia U, CS cisl.columbia.edu/faculty/shepard		design tools for advanced CMOS, SOI circuits, on-chip test and measurement circuitry, low-power design for DSP, CMOS gene chips dblp
Timothy Sherwood	Professor UC Santa Barbara CS cs.ucsb.edu/~sherwood		computer architecture, embedded systems, program phase behavior, SimPoint dblp
Olin Shivers	Professor Georgia Tech U, CS cc.gatech.edu/~shivers		advanced programming languages, systems, personal user interfaces, Scheme dblp
Sandeep K. Shukla	Professor Virginia Tech, ECE filebox.vt.edu/users/shukla		formal methods, system level power management, system level design and verification, ad-hoc networks dblp
Howard Jay Siegel	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~hj		parallel processing, heterogeneous computing, computer architecture, interconnection networks, parallel algorithms dblp
Daniel P. Siewiorek	Director of Human Computer-Interaction Institute Carnegie Mellon U cs.cmu.edu/~dps Eckert-Mauchly (1988) award		wearable computers, fault tolerance, CM* dblp
Gabriel M. Silberman	IBM Software Solutions Divisions, Toronto, Canada cas.ibm.com/director		computer architecture, compilers, digital circuit testing dblp
Jurij Silc	Researcher Jozef Stefan Institute, Ljubljana, Slovenia anica.ijs.si/silc		processor architecture, multithreaded computing, high-level synthesis, parallel processing, evolution algorithms dblp
Elizabeth A. Simon	Professor U of San Diego CS sandiego.edu/~bsimon		compilers, computer architecture, performance programming, scientific computing, EPIC compilation dblp
Tajana Simunic	Hewlett-Packard Labs akebono.stanford.edu/users/tajana/		system-level hardware and software design, wireless, embedded and low-power systems dblp
Jaswinder Pal Singh	Professor Princeton U, CS cs.princeton.edu/~jps		parallel architectures dblp
Montek Singh	Professor U of North Carolina CS cs.unc.edu/~montek		high-performance and low-power digital design, VLSI CAD, asynchronous circuits dblp
Satnam Singh	Microsoft Research xilinx.com/labs/satnam (old)		hardware description languages, formal verification for core verification, reconfigurable computing, layout analysis dblp
Henk J. Sips	Professor Delft U, Netherlands pds.twi.tudelft.nl/~henk		parallel algorithms, parallel computer architecture, parallel programming languages dblp
Mukund Sivaraman	R&D engineer Hewlett-Packard Labs, Compiler and Architecture Group hpl.hp.com/research/itc/car/Templates/mukund-sivaraman-page.html		timing and functional verification for ASIC, PICO dblp
Anand Sivasubramaniam	Professor Penn State U cse.psu.edu/~anand		computer architecture, operating systems, parallel computing, simulation and evaluation of dblp
Kevin Skadron	Professor U of Virginia, CS cs.virginia.edu/~skadron		HydraScalar, multipath execution dblp
Alexander Skavantzos	Professor Louisiana State U ece.lsu.edu/alex		computer arithmetic, computer architecture, ASIC design, VLSI signal processing, parallel processing dblp
Jonas Skeppstedt	Professor Lunds U, Sweden cs.lth.se/~js		compiler controlled data prefetching dblp
Konrad Slind	Professor U of Utah, CS cs.utah.edu/~slind		higher order logic, formal verification dblp
Yannis Smaragdakis	Professor Georgia Tech U, CS cc.gatech.edu/~yannis		object-oriented language design, tools to facilitate program construction, memory management dblp
Alan J. Smith	Professor UC Berkeley, CS cs.berkeley.edu/People/Faculty/Homepages/smith.html		caches, power management dblp
Burton J. Smith	Chief scientist Cray Inc Eckert-Mauchly (1991) award		high-performance computer architecture, parallel programming languages, MTA dblp
James E. Smith	Professor U of Wisconsin-Madison, ECE engr.wisc.edu/ece/faculty/smith_james.html Eckert-Mauchly (1999) award		Trace cache, Trace processor, Multiscalar dblp
Michael D. Smith	Professor Harvard U eecs.harvard.edu/~smith		Machsuif, compiler back-end dblp
Mark Smotherman	Professor Clemson U cs.clemson.edu/~mark		reliability, performance modeling, computer architecture dblp
Greg Snider	Hewlett-Packard Labs trimaran.org/car_group/greg_snider.html (old)		Elcor, compilation for reconfigurable hardware, PICO dblp
Marc Snir	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~snir		IBM Blue Gene, NYU Ultracomputer, MPI, IBM SP scalable parallel system, parallel algorithms, parallel architectures, interconnection networks, parallel programming environments dblp
Avinash Sodani	Intel, Hillsboro cs.wisc.edu/~sodani/sodani.html (old)		dynamic instruction reuse dblp
Mary Lou Soffa	Professor U of Virginia, CS cs.virginia.edu/~soffa		continuous and adaptive compilation, path and resource sensitive optimizations, experimental evaluation of optimizations, debugging optimized code, demand driven data flow, GUI testing dblp
Gurindar S. Sohi	Professor U of Wisconsin-Madison, CS cs.wisc.edu/~sohi Maurice Wilkes (1999) award		Multiscalar, speculative execution dblp
Yan Solihin	Professor North Carolina State U cesr.ncsu.edu/solihin		memory hierarchy organization, asymmetric architecture, customizable threads, processor-memory integration, self-optimizing systems dblp
Arun K. Somani	Professor Iowa State U, EE vulcan.ee.iastate.edu/~arun		fault tolerant computing, computer interconnection networks, optical networking, computer architecture, parallel computer systems dblp
Fabio Somenzi	Professor U of Colorado at Boulder, ECE vlsi.colorado.edu/~fabio		formal verification, CUDD, VIS, CAD, logic minimization dblp
Daniel J. Sorin	Professor Duke U, EE ee.duke.edu/~sorin		SMP, high availability servers, memory system design, verification of memory consistency, performance analysis dblp
Christos P. Sotiriou	Professor ICS-FORTH, Heraklion, Crete, Greece ics.forth.gr/~sotiriou		asynchronous circuit design and testing, industrial EDA tools for asynchronous design dblp
Jens Sparsø	Professor Technical U of Denmark imm.dtu.dk/~jsp		architecture and design of VLSI systems, asynchronous logic dblp
Evan Speight	Professor Cornell U, ECE csl.cornell.edu/~espeight		distributed computing, parallel processing, computer architecture, location-independent data access, operating systems dblp
Ellen Spertus	Professor Mills College mills.edu/ACAD_INFO/mcs_spertus.html		information retrieval, Internet, social issues, computer architecture, compilers dblp
Amitabh Srivastava	Vice President Microsoft research.microsoft.com/users/amitabhs		ATOM, programmer productivity, software engineering dblp
Richard M. Stallman	President Free Software Foundation stallman.org		Emacs, gcc, bison dblp
Mircea Stan	Professor U of Virginia, EE ee.virginia.edu/~mrs8n		low-power encoding methods and circuits, CAD for high-level power estimation, circuit design for novel low-power devices, low-power system integration dblp
Bjarne Steensgaard	Researcher Microsoft Research research.microsoft.com/~rusa		alias analysis, VDG, Java, C dblp
Darko Stefanovic	Professor U of New Mexico CS cs.unm.edu/~darko		dynamic cooperative performance optimization for Java, dynamic binary translation, computing with biochemical molecules dblp
J. Gregory Steffan	Professor U of Toronto, EE, Canada eecg.toronto.edu/~steffan		thread-level data speculation dblp
Bernhard Steffen	Professor U of Dortmund, Germany ls5-www.cs.uni-dortmund.de/staff/steffen.en.html		static analysis, lazy code motion, formal verification dblp
Per Stenström	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~pers		high-performance computers, multiprocessors for multimedia/database/numeric applications dblp
Thomas L. Sterling	Professor Caltech U cacr.caltech.edu/~tron		Beowulf, Hybrid Technology Multithreaded Architecture (HTMT), parallel computer architecture, system software, evaluation dblp
James E. Stine	Professor Illinois Institute of Technology, ECE ece.iit.edu/~jstine		computer arithmetic, computer architecture, VLSI, CAD techniques, reliable computing, compilers, digital circuit design, FPGA and DSP architectures dblp
Paul Stodghill	Research Associate Cornell U, CS cs.cornell.edu/stodghil		sparse compilation, sparse computations, fault-tolerance and dynamic resource management for scientific computations, extensible and open compiler systems, programming systems for HPC dblp
Mark G. Stoodley	U of Toronto, Canada eecg.toronto.edu/~stoodla		low-level compiler optimizations and related architectural features, vector microprocessors dblp
Quentin F. Stout	Professor U of Michigan eecs.umich.edu/~qstout		parallel and scientific computing, adaptive sampling designs, algorithms and data structures, operator theory and analysis dblp
Andrzej J. Strojwas	Professor Carnegie Mellon U, ECE ece.cmu.edu/people/show.php?type=faculty&id=171		design and manufacturing of ULSIC dblp
Bjarne Stroustrup	AT&T Research/Texas A&M U research.att.com/~bs/homepage.html ACM Grace Murray Hopper award (1983) award		C++ dblp
Volker Strumpen	Research scientist MIT cag.lcs.mit.edu/~strumpen		Porch: portable checkpoint compiler, Cilk, distributed operating systems, RAW operating system dblp
Michael Stumm	Professor U of Toronto, Canada eecg.utoronto.ca/~stumm		operating systems for distributed and parallel systems, multiprocessor architectures, DSM, parallel file systems, parallel compilers, Hector Multiprocessor, Hurricane OS, NUMAchine multiprocessor, Tornado OS dblp
Zhendong Su	Professor UC Davis, CS cs.ucdavis.edu/~su		static analyses for error detection dblp
Bronis R. de Supinski	Lawrence Livermore National Lab llnl.gov/CASC/people/de_supinski		cache coherence and distributed shared memory, consistency semantics, networks of workstations, distributed object computing, parallel and distributed simulation dblp
Ivan E. Sutherland	Sun sun.com/960710/feature3/ivan-profile.html Turing (1988) award, von Neumann medal, computer graphics award		asynchronous logic, micropipelines, Counterflow dblp
Bertil P. Svensson	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/People/svensson.html		parallel processing for embedded systems, distributed massively parallel architectures, neurocomputers, real-time systems dblp
Philip H. Sweany	Texas Instruments		compilation for VLIW dblp
Peter F. Sweeney	IBM Research T. J. Watson research.ibm.com/people/p/pfs/		analysis and optimization of object-oriented languages, software distribution dblp
Dennis Sylvester	Professor U of Michigan eecs.umich.edu/~dennis		modeling/characterization/analysis of deep submicron device technology dblp