Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Enrico Macii	Professor Politecnico di Torino, Italy eda.polito.it/enrico.html		CAD of digital integrated circuits and systems, logic synthesis/optimization/testing/formal verification, power estimation and optimization dblp
Kenneth M. Mackenzie	Adjunct Professor Georgia Tech U/Reservoir Labs cc.gatech.edu/~kenmac		Fugu, Alewife, soft architectures, active system-area networks dblp
David B. MacQueen	Professor U of Chicago cs.uchicago.edu/people/dbm		programming language design/definition/implementation, type and module systems, SML/NJ dblp
Tara M. Madhyastha	Professor UC Santa Cruz cse.ucsc.edu/~tara		high-bandwidth I/O interfaces, automatic performance characterization and adaptation dblp
Vijay K. Madisetti	Professor Georgia Tech, ECE users.ece.gatech.edu/~vkm/home.html		DSP, rapid prototyping, signal processors, VLSI CAD dblp
Bruce M. Maggs	Professor Carnegie Mellon U, CS cs.cmu.edu/~bmm		interconnection networks, parallels algorithms dblp
Nihar R. Mahapatra	Professor State U of New York at Bufallo cse.buffalo.edu/~mahapatr		computer architecture, parallel processing, VLSI, fault tolerance dblp
Rabi N. Mahapatra	Professor Texas A&M U, CS cs.tamu.edu/faculty/rabi		parallel and distributed computing, computer architecture, embedded system codesign dblp
Scott A. Mahlke	U of Michigan eecs.umich.edu/~mahlke		Trimaran, Elcor, EPIC, application-specific processor design, compilers, computer architecture, high-level synthesis dblp
Wai-Kei Mak	Professor National Tsing Hua U, Taiwan cs.nthu.edu.tw/~wkmak		VLSI CAD, discrete optimization, combinatorial optimization, computer architecture dblp
Miroslaw Malek	Professor Humboldt U Berlin, Germany informatik.hu-berlin.de/~malek		high-performance responsive computing, parallel architectures, real-time systems, networks, fault tolerance dblp
Sharad Malik	Professor Princeton U, EE ee.princeton.edu/~sharad/		CAD, Electronic Design Automation, design tools for embedded systems, hardware-software integration, digital circuit theory, synthesis and verification of digital systems dblp
Wojciech P. Maly	Professor Carnegie Mellon U, ECE ece.cmu.edu/~maly		VLSI design testing and manufacturing dblp
William H. Mangione-Smith	Professor UC Los Angeles icsl.ucla.edu/~billms		configurable computing systems, low power processor and system design, multimedia and communications processing, instruction-level parallelism, Mediabench dblp
Rajit Manohar	Professor Cornell U, ECE vlsi.cornell.edu/~rajit		asynchronous VLSI design, low energy design, architecture, concurrency, formal methods, programming language semantics, information theory dblp
Elias S. Manolakos	Professor Northeastern U, ECE cdsp.neu.edu/info/faculty/manolakos/manolakos.html		high performance computing, synthesis of parallel algorithms and architectures, pattern recognition and neural networks dblp
Panagiotis Manolios	Professor Georgia Institute of Technology cc.gatech.edu/~manolios		formal verification, theorem proving, model checking, abstraction, algorithms dblp
Olivier Maquelin	postdoc McGill U, Montreal, Canada cs.mcgill.ca/~maquelin (old)		multithreaded systems, EARTH dblp
Diana Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~dianam		energy-aware computing, low power CAD dblp
Radu Marculescu	Professor Carnegie Mellon U, ECE ece.cmu.edu/~radum		embedded systems, low-power CAD dblp
Malgorzata Marek-Sadowska	Professor U of California at Santa Barbara, ECE ece.ucsb.edu/Faculty/Marek-Sadowska/default.html		VAD for layout and logic synthesis, simulation of nonlinear circuits, timing verification dblp
Darko Marinov	Professor U of Illinois at Urbana-Champaign CS cag.lcs.mit.edu/~marinov		specification languages, checking code conformance, compilers, correctness of analyses and optimizations dblp
Evangelos P. Markatos	Professor U of Crete, Grece ics.forth.gr/~markatos		systems software for large scale multiprocessros, Psyche multiprocessor OS dblp
Igor L. Markov	Professor U of Michigan eecs.umich.edu/~imarkov		design of integrated circuits, quantum computing dblp
Marco Ajmone Marsan	Professor Politecnico di Torino, Italy www1.tlc.polito.it/ajmone		high-speed telecommunication networks, wireless and all-optical networks, performance evaluation of data communication and computer systems, Markovian models, queuing networks, generalized stochastic Petri nets dblp
Alain J. Martin	Professor Caltech U, CS cs.caltech.edu/cspeople/faculty/martin_a.html		asynchronous VLSI dblp
Milo M. K. Martin	Professor U of Pennsylvania cis.upenn.edu/~milom		computer architecture, multiprocessors, memory coherence dblp
Jose F. Martinez	Professor Cornell U, ECE csl.cornell.edu/~martinez		parallel computer architecture dblp
Margaret Martonosi	Professor Princeton U, EE ee.princeton.edu/~mrm		cache-decay, cache-miss equations, reconfigurable hardware (SAT) dblp
Peter Marwedel	Professor U of Dortmund, Germany ls12-www.cs.uni-dortmund.de/~marwedel		compilers for embedded processors, embedded software, high-level synthesis, test program generation for processors dblp
Peter M. Maurer	Professor U of South Florida csee.usf.edu/~maurer		VLSI design automation, VLSI design, software testing, computer architecture, parallel processing, FHDL, DGL dblp
John D. McCalpin	Senior Scientist IBM, Austin home.austin.rr.com/mccalpin		memory bandwidth, STREAM benchmark
Joel McCormack	Hewlett Packard WRL research.compaq.com/wrl/people/joel/bio.html		computer graphics, CAD dblp
Scott McFarling	Microsoft Research research.microsoft.com/~smcfar		profile-based optimization of memory performance, branch prediction dblp
Sally A. McKee	Professor Cornell U ECE csl.cornell.edu/~sam		processor and memory systems architecture, embedded systems, compilers, operating systems, performance analysis techniques and tools, Impulse dblp
Nick McKeown	Professor Stanford U, EE klamath.stanford.edu/~nickm		Tiny Tera, packet switches dblp
Kathryn S. McKinley	Professor U of Texas, Austin, CS cs.utexas.edu/users/mckinley		compilers, ParaScope dblp
Kenneth L. McMillan	Researcher Cadence Berkeley Labs www-cad.eecs.berkeley.edu/~kenmcmil		formal verfication, symbolic model checking, SMV dblp
Carver A. Mead	Professor (emeritus)/Chairman Caltech U/Foveon foveon.com/about_executive.html Allen Newel (1997) award, von Neumann Medal		semiconductors, physics of computation dblp
Eduard Mehofer	Professor U of Viena, Austria par.univie.ac.at/~mehofer		optimising compilers, parallel and distributed computing, communication optimizations, feedback-directed compilation, grid computing dblp
Nagi N. Mekhiel	Professor Ryerson Polytechnic U, Canada ee.ryerson.ca/~nmekhiel		computer architecture and parallel processing, high performance memory systems, VLSI, performance evaluation
Waleed M. Meleis	Professor Northeastern U, ECE ece.neu.edu/faculty/meleis.html		code scheduling dblp
Rami G. Melhem	Professor U of Pittsburgh, CS cs.pitt.edu/~melhem		fault-tolerant systems, optical networks, real-time parallel and distributed systems, power aware computing dblp
John M. Mellor-Crummey	Professor Rice U, CS cs.rice.edu/~johnmc		software support for HCP, multiprocessor synchronization, parallel debugging, parallel operating systems, parallelizing compilers, compiler and run-time techniques for improving memory hierarchy performance dblp
Gokhan Memik	Professor Northwestern U ECE ece.northwestern.edu/~memik		application-specific programmable processors, compilers, embedded systems, microarchitecture dblp
Oskar Mencer	Professor Imperial College, UK/Bell Labs, Lucent doc.ic.ac.uk/~oskar/		general computer architecture, custom computing, FPGAs, computer arithmetic, domain-specific compilers, low-power computing, CAD and VLSI dblp
Bilha Mendelson	Manager, Code optimization group IBM Research Lab, Haifa, Israel		code optimization, compiler optimization, modern computer architecture dblp
Teresa H. Meng	Professor Stanford U, ECE dualist.stanford.edu/~thm		low-power circuit and system design, video signal processing, wireless communications, circuit optimization, neural signal processing, computation architectures for future CMOS technology, Atheros Communications dblp
José Meseguer	Professor U of Illinois at Urbana-Champaign, CS formal.cs.uiuc.edu/meseguer/		declarative languages, OBJ, Maude, formal specification and verification, concurrency theory, parallel software and architectures for declarative languages, logical foundations of computer science dblp
David G. Messerschmitt	Professor UC Berkeley, ECE eecs.berkeley.edu/~messer		technology/economy/business, DSP, networking, VLSI, signal processing dblp
David G. Meyer	Professor Purdue U, ECE digibowser.ecn.purdue.edu/dsl/meyer.html		instructional multimedia, technology-based education, computer architecture and parallel processing, microprocessor system design and interfacing, electro-acoustics dblp
Dirk Meyer	senior vice president AMD corp. Maurice Wilkes (2003) award		Athlon, Opteron, Alpha 21064, 21264
Maged M. Michael	IBM T. J. Watson cs.rochester.edu/u/michael (old)		distributed shared memory dblp
Pierre Michaud	Researcher IRISA, France irisa.fr/caps/people/michaud/index_fr.htm		computer architecture dblp
Giovanni De Micheli	Professor Stanford U, ECE akebono.stanford.edu/users/nanni		CAD, digital circuits, hw/sw codesign, VLSI dblp
Samuel P. Midkiff	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~smidkiffw		high performance compilers, programming environments and tools, compilation of explicitly parallel programs, utility of consistency models, compiling for safety and repeatability, Polaris, Numeric Java dblp
Robin Milner	Professor U of Cambridge, UK cl.cam.ac.uk/users/rm135 Turing (1991) award		LCF, ML, CCS dblp
Veljko M. Milutinovic	Professor U of Belgrade, Serbia, Yugoslavia galeb.etf.bg.ac.yu/~vm		Internet, infrastructure for Electronic Business on Internet, SMP and DSM, VLSI, microprocessor architecture/design, FPGA, silicon compilation dblp
Jayadev Misra	Professor U of Texas, Austin, CS cs.utexas.edu/users/misra		formal methods, specifications/designs of synchronous/asynchronous systems, UNITY dblp
Markus U. Mock	Professor U of Pittsburgh, CS cs.pitt.edu/~mock		compilers and computer architecture, (run-time) program optimization, static and dynamic program analysis dblp
Adrian Moga	Sequent Computer Systems Inc usc.edu/dept/ceng/dubois/moga/moga.html (old)		DSM, hardware emulation dblp
Saraju P. Mohanty	Professor U of North Texas cs.unt.edu/~smohanty		CAD for nanoscale VLSI, synthesis and optimization for low power, power-aware system design, VLSI architectures for security and DRM dblp
Aloysius K. Mok	Professor U of Texas at Austin cs.utexas.edu/users/mok		fault-tolerant hard-real-time systems, system architecture, computer-aided system design tools, software engineering dblp
Dan I. Moldovan	Professor U Texas at Dallas utdallas.edu/~moldovan		systolic processors, natural language processing, machine learning, artificial intelligence, parallel and distributed processing dblp
Charles E. Molnar	(deceased) U of Washington in St. Louis /www.cse.wustl.edu/history/molnar_c		asynchronous circuits, metastability, LINC, audio signals and neural responses, biomedical computing dblp
Burkhard Monien	Professor U Paderborn, Germany uni-paderborn.de/fachbereich/AG/monien/PERSONAL/bm.html		parallel computation, parallel architecture, scientific computing, interconnection networks dblp
Soo-Mook Moon	Professor Seoul National U, Korea ee.snu.ac.kr/english/faculty/moon-soomook.htm		system software, microprocessor structure, superpipelining dblp
Oege de Moor	Professor Oxford U, UK web.comlab.ox.ac.uk/oucl/people/oege.demoor.html		intentional programming, transformation of Haskell programs, algebra of programming, predicate transformers, compositional logic programming, complexity and programming languages dblp
Gordon E. Moore	Chairman Emeritus of the Board Intel developer.intel.com/pressroom/kits/bios/moore.htm		Moore's law, Intel dblp
J. Strother Moore	Professor U of Texas, Austin, CS cs.utexas.edu/users/moore		theorem prooving, Boyer-Moore theorem prover, hardware and software verification, ACL2 dblp
Edward David Moreno	Professor U of Sao Paulo, Brazil lsi.usp.br/~edmoreno		computer architecture, performance evaluation and analysis, Petri nets, computer networks, reconfigurable hardware dblp
Jaime H. Moreno	IBM T. J. Watson		processor architecture, ILP, embedded systems, systolic matrix computations dblp
Csaba Andras Moritz	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/andras		Cool-*: compiler-enabled power-aware microprocessor architecture, self-evolving software/hardware dblp
John Morris	Professor U of Western Australia ciips.ee.uwa.edu.au/~morris		high performance parallel processors, reconfigurable processors, networks of workstations, fault-tolerant Cilk, Achilles high-bandwidth interconnect, asynchronous logic, software verification dblp
Andreas Moshovos	Professor U of Toronto, EE, Canada eecg.toronto.edu/~moshovos		PACT, SHARPP, slice processors, memory dependence speculation dblp
J. Eliot B. Moss	Professor U of Massachusetts, Amherst www-osl.cs.umass.edu/~moss		programming language design and implementation, database and information retrieval systems, persistent object stores and persistent programming languages, memory management and garbage collection dblp
Todd C. Mowry	Professor Carnegie Mellon U, CS cs.cmu.edu/~tcm		Thread-Level Data Speculation, Stampede, software prefetching dblp
Steven S. Muchnick			compilers dblp
Trevor N. Mudge	Professor U of Michigan eecs.umich.edu/~tnm		PowerAnalyzer, instruction stream compression, microprocessor verification, high performance computing dblp
Frank Mueller	Professor North Carolina State U moss.csc.ncsu.edu/~mueller		compilers, real-time systems, parallel and distributed systems dblp
Silvia M. Mueller	U des Saarlandes, Germany www-wjp.cs.uni-sb.de/~smueller		complexity and correctness of computer architectures, parallel architectures: design / modelling / performance, parallelization of algorithms, hardware support for multimedia dblp
Shubhendu S. Mukherjee	Hewlett Packard cs.wisc.edu/~shubu/shubu.html (old)		network interfaces, coherence protocols dblp
Hans Mulder	Senior Principal Engineer Intel Research intel.com/research/people/bios/mulder_h.htm		Itanium, distributed systems, ubiquitous computing dblp
Henk Muller	Reader U of Bristol, UK cs.bris.ac.uk/~henkm		data diffusion machine, trivial mobile software, PRISMA, DOOM dblp
Jean-Michel Muller	senior researcher Ecole Normale Superieure de Lyon, France ens-lyon.fr/~jmmuller		algorithms and architectures for fast and/or accurate arithmetic, number systems, elementary functions, Cordic dblp
Markus Müller-Olm	Research assistant Dortmund U, Germany sunshine.cs.uni-dortmund.de/~mmo		analysis and verification of programs and systems dblp
Kazuaki Murakami	Professor Kyushu U, Japan kasuga.csce.kyushu-u.ac.jp/~murakami		computer system architecture, parallel computing/processing, compiling for parallel architectures, performance evaluation, architecture/hardware modeling and optimization dblp
Saburo Muroga	Professor (emeritus) U of Illinois Urbana-Champaign, ECE cs.uiuc.edu/contacts/faculty/muroga.html		CAD, Transduction, SYLON dblp
Chris J. Myers	Professor U of Utah, ECE shang.elen.utah.edu/~myers		design methods and tools for VLSI systems, asynchronous circuit design, formal timing verification, design of analog decoders dblp