Researchers in Computer Architecture and Compilers

http://www.cs.cmu.edu/~mihaib/whoswho

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Name Address Picture Work
C
Goto: all A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
George Z. N. Cai Engineering manager
Intel Design Center, Texas
? power modeling and management,
microprocessor design and implementation
dblp
Brad Calder Professor
UC San Diego
www-cse.ucsd.edu/users/calder
Brad Calder prediction,
mobile code,
PSSA
dblp
Timothy J. Callahan post-doc
Carnegie Mellon U, CS
www-2.cs.cmu.edu/~tcal
Timothy J. Callahan GARP,
reconfigurable hardware compilation,
system-on-a-chip design automation,
hardware/software codesign
dblp
João M. P. Cardoso Professor
U of Algarve, Portugal
w3.ualg.pt/~jmcardo
João M. P. Cardoso reconfigurable computing,
high-level synthesis for FPGAs,
design automation for embedded systems
dblp
Douglas M. Carmean principal engineer/architect
Intel Desktop Products, Oregon
Douglas M. Carmean IA-32,
Pentium,
Pentium 4
dblp
Steven M. Carr Professor
Michigan Technological U, CS
cs.mtu.edu/~carr
Steven M. Carr high-level optimization for DSP,
compilers-computer architecture interaction,
concurrent computing
dblp
John B. Carter Professor
U of Utah, CS
cs.utah.edu/~retrac
John B. Carter operating systems,
parallel and distributed computing,
multiprocessor computer architecture,
memory system design,
Munin
dblp
Lori Carter Professor
Point Loma Nazarene U, San Diego
mcs.ptloma.edu/Carter
Lori Carter computer architecture,
compiler optimizations,
predicated execution,
compilation for IA64
dblp
Nicholas P. Carter Professor
U of Illinois Urbana-Champaign, ECE
crhc.uiuc.edu/~npcarter
Nicholas P. Carter reconfigurable logic,
computing using non-silicon
dblp
Calin Cascaval IBM T. J. Watson
polaris.cs.uiuc.edu/~cascaval (old)
Calin Cascaval parallel compilers,
parallel and distributed computing,
object oriented compilers and methodologies
dblp
Steve Casselman Virtual Computer Corp
? reconfigurable computing,
search engines
dblp
Gregory J. Chaitin IBM T. J. Watson
cs.umaine.edu/~chaitin
Gregory J. Chaitin register allocation,
algorithmic information theory
dblp
Craig Chambers Professor
U of Washington Seattle, CS
cs.washington.edu/homes/chambers
Craig Chambers SPIN,
dynamic compilation,
Vortex,
Cecil
dblp
Fay Chang Google
cs.cmu.edu/~fwc (old)
? Speculative prefetching for disk data,
distributed filesystems
dblp
J. Morris Chang Professor
Iowa State U, EE
vulcan.ee.iastate.edu/~morris
J. Morris Chang wireless network,
computer architecture,
object-oriented programming languages,
memory management,
hardware description languages,
internet architecture
dblp
Craig M. Chase Professor
U of Texas, Austin, ECE
ece.utexas.edu/~chase
Craig M. Chase parallel architectures and algorithms
dblp
Siddhartha Chatterjee Professor
U of North Carolina, CS
cs.unc.edu/~sc
Siddhartha Chatterjee cache-conscious algorithms,
data parallelism
dblp
Tiberiu Chelcea postdoc
Carnegie Mellon U, CS
cs.cmu.edu/~tibi
Tiberiu Chelcea asynchronous circuits
dblp
Peter M. Chen Professor
U of Michigan
eecs.umich.edu/~pmchen
Peter M. Chen RIO,
ARMADA,
fault tolerance,
disk systems
dblp
Tien-Fu Chen Professor
National Chung Cheng U, China
cs.ccu.edu.tw/~chen
Tien-Fu Chen computer architecture,
SOC design,
embedded systems
dblp
Fu-Chiung John Cheng Professor
Tatung U, Taiwan
cse.ttu.edu.tw/~cheng
Fu-Chiung John Cheng Systems-on-a-chip,
hardware-software codesign,
CAD tools,
asynchronous logic,
FPGAs,
Java-enabled embedded systems,
real-time OS,
expert database systems
dblp
Perry Cheng IBM T.J. Watson
research.ibm.com/people/p/perryche
Perry Cheng garbage collection,
type-directed compilation
dblp
David R. Cheriton Professor
Stanford U
www-dsg.stanford.edu/DavidCheriton.html
David R. Cheriton distributed systems,
high performance networks,
operating systems,
distributed interactive simulation,
object-oriented design techniques
dblp
Peter Y. K. Cheung Professor
Imperial College, London, UK
ee.ic.ac.uk/pcheung
Peter Y. K. Cheung reconfigurable computing,
hardware/software codesign,
CAD,
Digital and Asynchronous Systems,
VLSI architecture for signal processing,
mixed signal designs
dblp
Men-Chow Chiang IBM Server Group
? memory systems for multiprocessors
dblp
Donald M. Chiarulli Professor
U of Pittsburgh, EE
cs.pitt.edu/~don
Donald M. Chiarulli chip level optoelectronic interconnections,
optical-electronic-mechanical multi-domain CAD,
optical memory systems,
robotics,
SOC voice based interfaces
dblp
Andrew A. Chien Professor
UC San Diego
www-csag.ucsd.edu/individual/achien/achien.html
Andrew A. Chien Agile Distributed Objects,
High Performance Virtual Machines (HPVM),
Illinois Concert Project,
QoS management
dblp
Bruce R. Childers Professor
U of Pittsburgh, CS
cs.pitt.edu/~childers
Bruce R. Childers automatic design of application-specific processors,
custom VLIW/systolic architectures,
low-power embedded processors,
computer architecture,
compilers and software development tools
dblp
Trishul M. Chilimbi Microsoft Research
research.microsoft.com/~trishulc
Trishul M. Chilimbi optimizations for caching
dblp
Giovanni Chiola Professor
U di Genova, Italy
disi.unige.it/person/ChiolaG
Giovanni Chiola active messages (GAMMA),
distributed databases
dblp
Derek Chiou Professor
U of Texas at Austin ECE
ece.utexas.edu/~derek
Derek Chiou simulators,
sequential and parallel computer architectures,
router architecture,
dataflow machines,
StarT
dblp
Jong-Deok Choi IBM Research T. J. Watson
research.ibm.com/people/j/jdchoi
? programming languages,
compiler optimizations,
software engineering
dblp
Kiyoung Choi Professor
Seoul National U, Korea
poppy.snu.ac.kr/~kchoi/kchoi.html
Kiyoung Choi VLSI design,
CAD,
hardware-software codesign,
high-level synthesis,
low-power system design
dblp
Frederic T. Chong Professor
UC Davis, CS
american.cs.ucdavis.edu:80/~chong
Frederic T. Chong Active Pages
dblp
Pai H. Chou Professor
UC Irvine
ece.uci.edu/~chou
Pai H. Chou IMPACCT,
embedded systems,
low power design
dblp
Alok N. Choudhary Professor
Northwestern U ECE
ece.northwestern.edu/~choudhar
Alok N. Choudhary compilers and runtime systems for high-performance embedded/adaptive/power-aware systems,
high-performance databases,
parallel and high-performance storage and I/O systems
dblp
Fred C. Chow Pathscale, Inc.
? optimizing compilers
dblp
Paul Chow Professor
U of Toronto, EE, Canada
eecg.toronto.edu/~pc
Paul Chow FPGAs,
OneChip,
Transmogrifier-2
dblp
Giuseppe Ciaccio Professor
U di Genova, Italy
disi.unige.it/person/CiaccioG
Giuseppe Ciaccio clusters of PCs,
operating systems,
parallel processing,
parallel computer architecture
dblp
Michal Cierniak researcher
Intel Microprocessor Research Labs, Programming Systems Lab
intel.com/research/mrl/people/cierniak_m.htm
Michal Cierniak virtual machines,
runtime systems,
just-in-time compilation,
high-performance compiler optimizations
dblp
Marcelo H. Cintra Professor
U of Edinburgh, UK
dcs.ed.ac.uk/home/mc
Marcelo H. Cintra computer architectures,
parallel and high-performance computing,
scientific computing
dblp
Douglas W. Clark Professor
Princeton U, CS
cs.princeton.edu/~doug
Douglas W. Clark processor architecture and organization,
performance measurement and analysis,
computer architecture,
Display Wall
dblp
Wesley A. Clark Clark, Rockoff and Associates

Eckert-Mauchly (1981) award
Wesley A. Clark design of early computers,
TX-0,
TX-2
dblp
Edmund M. Clarke Professor
Carnegie Mellon U, CS
cs.cmu.edu/~emc
Edmund M. Clarke formal verification,
model checking
dblp
John G. Cleary Professor
U of Waikato, New Zealand
cs.waikato.ac.nz/Staff/john-g.-cleary.html
John G. Cleary parallel and distributed systems,
TimeWarp,
compression,
logic programming
dblp
Cliff Click Motorola
crpc.rice.edu/MSCP/cliff.html (old)
Cliff Click compiler optimizations,
intermediate program representations
dblp
John Cocke (deceased)
IBM T. J. Watson

Eckert-Mauchly (1985) award, Turing (1987) award
John Cocke optimizing compilers,
RISC processors
dblp
Robert S. Cohn Intel
Robert S. Cohn Alpha compilers,
profile-feedback compilation,
Spike,
code layout in Unix OM
dblp
Michele Colajanni Professor
U di Modena, Italy
traianus.ce.uniroma2.it/people/colajanni.html
Michele Colajanni distributed parallel computing,
distributed web servers,
parallel scientific computing,
fault-tolerance,
interconnection networks,
performance analysis and simulation
dblp
Osvaldo Colavin ST Microelectronics
? architectural support for multimedia
dblp
Jean-Francois Collard Intel
prism.uvsq.fr/~jfcollar (old)
Jean-Francois Collard automatic parallelization,
optimizing compilers
dblp
Robert P. Colwell Colwell and Associates, Inc.

Eckert-Mauchly (2005) award
Robert P. Colwell Pentium Pro,
Multiflow
dblp
Hubert Comon-Lundh Professeur
Ecole Normale Superieure de Cachan, France
lsv.ens-cachan.fr/~comon/
Hubert Comon-Lundh term rewriting,
symbolic constraint solving,
tree automata techniques,
verification of infinite state systems,
cryptographic protocols
dblp
Katherine Compton Professor
U of Wisconsin-Madison ECE
ece.wisc.edu/~kati/
Katherine Compton reconfigurable computing
dblp
Jason Cong Professor
U of California at Los Angeles, CS
ballade.cs.ucla.edu/~cong
Jason Cong hardware synthesis,
giga-scale system-on-a-chip,
FPGAs,
large-scale CAD
dblp
Daniel A. Connors Professor
U of Colorado, CS
cs.colorado.edu/~dconnors
Daniel A. Connors high performance computer systems,
run-time optimization architectures,
embedded systems,
optimizing compilers,
operating systems
dblp
Charles Consel Professor
ENSEIRB/LaBRI/INRIA Bordeaux, France
compose.labri.u-bordeaux.fr/people/consel
Charles Consel programming languages,
program analysis and transformation,
software engineering,
operating systems
dblp
Thomas M. Conte Professor
North Carolina State U, ECE
tconte.org
Thomas M. Conte compiler design,
advanced microarchitectures,
VLIW/IA-64 compilers
dblp
Lynn Conway Professor (emeritus)
U of Michigan
ai.eecs.umich.edu/people/conway/conway.html
Lynn Conway VLSI,
robotics/AI
dblp
Stephen A. Cook Professor
U of Toronto, CS, Canada
cs.toronto.edu/~sacook
Turing (1982) award
Stephen A. Cook NP-completeness,
computational complexity,
logic
dblp
William R. Cook Professor
U of Texas at Austin, CS
cs.utexas.edu/users/wcook
William R. Cook programming languages,
mixins,
type theory,
object-oriented programming,
interfacing languages and databases,
software engineering,
web-based information systems,
information security
dblp
Keith D. Cooper Professor
Rice U, CS
cs.rice.edu/~keith
Keith D. Cooper Rn,
ParaScope,
low-level code optimization,
code generation,
GrDAS
dblp
Lee D. Coraor Professor
Penn State U
cse.psu.edu/gradbroc/faculty/coraor.html
Lee D. Coraor FPGAs,
SmartDIMM (computing in memory)
dblp
Henk Corporaal Professor
Technische U Eindhoven, Netherlands
ics.ele.tue.nl/~heco
Henk Corporaal automatic synthesis of application specific processors,
very large scale distributed embedded DSP systems
dblp
Jordi Cortadella Professor
U Politecnica de Catalunya, Spain
lsi.upc.es/~jordic
Jordi Cortadella synthesis,
analysis and verification of concurrent systems,
asynchronous systems,
logic synthesis,
Petrify
dblp
Michel Cosnard Professor/director
INRIA
inria.org/presse/cvmc.en.html
Michel Cosnard parallel algorithms and architectures,
algorithm complexity,
automata theory and neural networks,
discrete dynamical systems
dblp
Patrick Cousot Professor
Ecole Normale Superieure Paris, France
di.ens.fr/~cousot
Patrick Cousot abstract interpretation,
semantics
dblp
Radhia Cousot Research Director
Ecole Polytechnique, France
di.ens.fr/~cousot
? abstract interpretation,
semantics,
proofs
dblp
Alan L. Cox Professor
Rice U, CS
cs.rice.edu/~alc
Alan L. Cox TreadMarks,
FASTLINK
dblp
Harvey G. Cragon Professor (emeritus)
U of Texas, Austin, ECE
ece.utexas.edu/ece/people/profs/Cragon.html
Eckert-Mauchly (1986) award
Harvey G. Cragon first integrated circuit computer,
first TTL computer
dblp
Karl Crary Professor
Carnegie Mellon U, CS
cs.cmu.edu/~crary
Karl Crary type-oriented compilation strategies,
type-based certification of mobile code,
high-level programming language design
dblp
John Crawford Director of McKinley Architecture
Intel Architecture Group, Enterprise Platforms Group
intel.com/pressroom/kits/bios/crawford.htm
Eckert-Mauchly (1995) award
John Crawford IA-64,
80386,
Pentium
dblp
Seymour Cray (deceased)
cgl.ucsf.edu/home/tef/cray/tribute.html
Eckert-Mauchly (1989) award
Seymour Cray supercomputers
Stefano Crespi-Reghizzi Professor
Politecnico di Milano, Italy
elet.polimi.it/people/crespi
Stefano Crespi-Reghizzi formal languages and automata,
compiler optimization and parallelization,
programming languages,
man-machine interfaces
dblp
Darren C. Cronquist Hewlett-Packard Labs, Compiler and Architecture Group
hpl.hp.com/research/itc/car/Templates/darren-cronquist-page.html
Darren C. Cronquist architectures/compilers/languages for embedded applications,
RaPiD (reconfigurable hardware),
PICO
dblp
Mark Crovella Professor
Boston U, CS
cs-www.bu.edu/faculty/crovella
Mark Crovella performance evaluation of parallel and networked computers,
measuring and characterizing the web
dblp
David E. Culler Professor
UC Berkeley, CS
cs.berkeley.edu/~culler
David E. Culler Active Messages,
Threaded Abstract Machine,
parallel architectures
dblp
Walling R. Cyre Professor
Virginia Tech, EE
ecpe.vt.edu/faculty/cyre.html
Walling R. Cyre automatic design,
requirements analysis,
natural language understanding,
automatic modeling,
high-level synthesis,
design representation
dblp
Ronald K. Cytron Professor
Washington U in St. Louis, CS
cs.wustl.edu/~cytron
Ronald K. Cytron SSA,
compilers,
continuous compilers,
packet filtering,
secure voting
dblp