Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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M. Frans Kaashoek	Professor MIT pdos.lcs.mit.edu/~kaashoek		Click modular router, Exokernel, tick-C, Amoeba/Orca dblp
Péter Kacsuk	head of the Parallel and Distributed Systems Laboratory Computer and Automation Research Institute of the Hungarian Academy of Sciences ultra10.lpds.sztaki.hu/staff/kacsuk_peter/sajat_honlap		paralel logic programming, parallel computer architectures, parallel software engineering, Grid tools dblp
David R. Kaeli	Professor Northeastern U, ECE ece.neu.edu/faculty/kaeli.html		branch prediction, I/O workload characterization, memory hierachy design, object-oriented code performance, 3-D VLSI design, compiler back-ends, trace-driven simulation dblp
Alain Kägi	Researcher Intel Microprocessor Research Labs intel.com/research/mrl/people/kagi_a.htm		memory bandwith, optimized synchronization dblp
Krishnan Kailas	research staff IBM T. J. Watson e-kailas.net		low-power embedded architectures and DSP, microarchitecture and compilation for Clustered ILP processors dblp
Samuel N. Kamin	Professor U of Illinois at Urbana-Champaign, CS www-sal.cs.uiuc.edu/~kamin		programming languages, software components, functional programming applied to scientific computation, denotational semantics, program specification and verification, domain-specific languages dblp
Mahmut Taylan Kandemir	Professor Penn State U cse.psu.edu/~kandemir		embedded systems, optimizing compilers, power-aware computing, multi-dimensional databases dblp
Russell Kao	senior staff engineer Sun Research research.sun.com/people/rkao		computer architecture, CAD, HP-PA, mixed switch-level/circuit level simulation dblp
Wolfgang Karl	Professor Muenchen Technical U, Germany wwwbode.cs.tum.edu/~karlw		computer architecture, microprocessors, computer and systems design, parallel and distributed systems, DSM, scalable coherent interface, fault tolerance, high availability, hot-swap, cache architectures, reconfigurable computing dblp
Hironori Kasahara	Professor Waseda U, Tokio, Japan kasahara.elec.waseda.ac.jp/kasahara.en.html		supercomputing, multiprocessor architectures, scheduling algorithms, parallelizing compilers, electronic circuit simulation dblp
Daniel Kästner	Senior Software Engineer AbsInt GmbH rw4.cs.uni-sb.de/~kaestner		embedded systems, retargetable compiler construction, code generation and optimization, generative programming, Java, integer linear programming, program analysis, scheduling, document processing dblp
Ryan Kastner	Professor UC Santa Barbara ECE ece.ucsb.edu/~kastner		embedded systems, reconfigurable computing, compilers, sensor networks dblp
Manolis G. H. Katevenis	Professor U of Crete, Grece archvlsi.ics.forth.gr/~kateveni		packet switch architecture, high-speed networks, computer architecture, VLSI dblp
Vinod Kathail	R&D Program Manager Hewlett-Packard trimaran.org/car_group/vinod_kathail.html (old)		Trimaran, PICO, EPIC, Elcor dblp
Srinivas Katkoori	Professor U of South Florida vcapp.csee.usf.edu/~katkoori		high level synthesis, low power synthesis, VLSI CAD for deep sub-micron regime, reconfigurable computing for space applications dblp
Joost-Pieter Katoen	Professor RWTH Aachen University, Germany www-i2.informatik.rwth-aachen.de/~katoen		semantics, probabilistic verification, software verification, process algebra, formal specification dblp
Randy H. Katz	Professor UC Berkeley, CS cs.berkeley.edu/~randy		network computing, communications-oriented service architectures dblp
Alireza Kaviani	Xilinx Research eecg.toronto.edu/~kaviani (old)		FPGA design dblp
Stefanos Kaxiras	Professor U of Patras, Greece cs.wisc.edu/~kaxiras		SMP, cache decay, Datascalar dblp
Tom Kean	Director Algotronix Ltd. algotronix.com/people/tom		Xilinx XC6200 FPGA architecture, reconfigurable computing dblp
Stephen W. Keckler	Professor U of Texas, Austin, CS cs.utexas.edu/users/skeckler		M-Machine, VLSI circuit design dblp
Gershon Kedem	Professor Duke U, CS kedem.cs.duke.edu		high performance memory systems dblp
Diana Keen	Professor Cal Poly csc.calpoly.edu/~dkeen		computer architecture, compilers, intelligent memory dblp
Robert M. Keller	Professor Harvey Mudd College cs.hmc.edu/~keller		programming languages: functional/parallel/real-time/logic, genetic programming dblp
Paul H. J. Kelly	Reader Imperial College of Science, Technology and Medicine, London, UK doc.ic.ac.uk/~phjk		computer systems issues underlying performance, performance evaluation / modelling / prediction, languages, compilers and operating systems for parallel computing dblp
Ken Kennedy	Professor Rice U, CS cs.rice.edu/~ken		vectorization, ParaScope, HPF, HPC dblp
Brian W. Kernighan	professor Princeton U, CS cs.princeton.edu/~bwk		C, programming, AWK, AMPL dblp
Christoph W. Keßler	Professor Linkoping U, Sweden ida.liu.se/~chrke/		parallel computing, compilers for instruction-level parallel and embedded processors, automatic parallelization dblp
Richard E. Kessler	Hewlett-Packard Research		processor caches, performance evaluation dblp
Kurt Keutzer	Professor UC Berkeley, EE www-cad.eecs.berkeley.edu/~keutzer		MESCAL, embedded processor compilation, logic synthesis, test and timing verification, BACPAC dblp
Tom Kilburn	Professor (deceased) U of Manchester, UK computer50.org/mark1/kilburn.html Eckert-Mauchly (1981) award		Mark1, MUSE/Atlas, MU5 dblp
Earl Killian	Chief Architect Tensilica killian.com/earl		Pixie, processor architecture, MIPS, finger, SMTP dblp
Eun Jung Kim	Professor Texas A&M U, CS faculty.cs.tamu.edu/ejkim		computer architecture, power efficient systems, parallel/distributed systems, computer networks, cluster computing, QoS support in cluster networks and Internet, performance evaluation, fault-tolerant computing dblp
Shin-Dug Kim	Professor Yonsei U, Korea supercom.yonsei.ac.kr/~sdkim		advanced computer architectures, parallel processing systems, memory system design, heterogeneous Web computing, agent based Internet computing dblp
Taewhan Kim	Professor KAIST, Korea vlsisyn.kaist.ac.kr/~tkim		embedded system design, architecture-level synthesis for system-on-chip, logic-level synthesis, high-level synhesis, routing for FPGAs dblp
David Kinniment	Professor U of Newcastle upon Tyne EE, UK staff.ncl.ac.uk/david.kinniment/		synchronization, arbitration, metastability, asynchronous design, computer systems and microelectronics education dblp
Michael Kishinevsky	Strategic CAD Labs, Intel intel.com/research/people/bios/kishinevsky_m.htm		high-level and asynchronous design, reactive systems, theory of concurrency dblp
Artur Klauser	Intel, VSSAD cs.colorado.edu/~klauser (old)		ILP, computer architecture and microarchitecture, compiler optimizations, operating systems, distributed and parallel systems, high-performance computing, multipath execution dblp
Tom Knight	Professor MIT ai.mit.edu/people/tk/tk.html		microbial engineering, reversible and low energy computing, VLSI microdisplays, Abacus (SIMD), transit, transactional execution of programs dblp
Jens Knoop	Professor U of Viena, Austria complang.tuwien.ac.at/knoop		lazy code motion, programming languages and compilers, formal methods, program analysis/verification/optimisation/tools, Internet dblp
Donald E. Knuth	Professor (emeritus) Stanford U, CS www-cs-faculty.stanford.edu/~knuth Turing (1974) award, National Medal of Science (1979)		parsing, Algol 60, profiling, TeX, algorithms dblp
Seok-Bum Ko	Professor U of Saskatchewan EE, Canada engr.usask.ca/~sek867		FPGA, microprocessors dblp
Peter M. Kogge	Professor Notre Dame U nd.edu/~kogge		massively parallel processing architectures, advanced VLSI technology and architectures, parallel algorithms and applications, processing in memory dblp
Cheng-Kok Koh	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~chengkok/		layout-driven synthesis, interconnect-driven floorplanning and placement, global routing, clock synthesis, reduced-order modeling, power-supply network analysis and synthesis, very-high performance circuit design and synthesis dblp
Philip Koopman	Professor Carnegie Mellon U, ECE ece.cmu.edu/~koopman		Ballista, embedded Computing, stack machines, Forth dblp
David M. Koppelman	Professor Louisiana State U ece.lsu.edu/koppel		interconnection networks, multiprocessors dblp
Israel Koren	Professor U of Massachusetts, Amherst ecs.umass.edu/ece/koren		VLSI yield, CAD for yield estimation and reliability, fault tolerance in real-time systems, computer arithmetic dblp
Nectarios G. Koziris	Professor National Technical U of Athens, Greece cslab.ece.ntua.gr/~nkoziris		parallel processing, parallel architectures, distributed systems, computer architecture dblp
Christoforos E. Kozyrakis	Professor Stanford U csl.stanford.edu/~christos		microprocessor architecture and design, IRAM dblp
Andreas Krall	Professor Technische U Wien, Austria complang.tuwien.ac.at/andi/home.html		object oriented languages, compiler back ends and computer architecture, logic programming, compilation for embedded processors dblp
Ulrich Kremer	Professor Rutgers U, CS athos.rutgers.edu/~uli		power and energy management, distributed embedded systems, compilation, data layout, performance prediction models dblp
Chandra Krintz	Professor UC Santa Barbara, CS cs.ucsb.edu/~ckrintz		adaptive compilation, mobile Java code dblp
Daniel Kroening	postdoc Carnegie Mellon U kroening.com		computer architecture, formal verification dblp
John D. Kubiatowicz	Professor UC Berkeley, CS cs.berkeley.edu/~kubitron		IRAM, Oceanstore, Alewife, quantum computers dblp
William J. Kubitz	Professor (emeritus) U of Illinois at Urbana-Champaign, CS cs.uiuc.edu/people/faculty/kubitz.html		VLSI physical design, computer graphics, converged media, mobile/wireless dblp
David J. Kuck	Chairman Kuck and Associates, Inc Eckert-Mauchly (1993) award, Charles Babbage award		parallel architectures, scientific computation, paralellizing compilers, Parafrase, KAP, KAI dblp
Philip J. Kuekes	Hewlett-Packard Labs hpl.hp.com/research/qsr/staff/kuekes.html		Teramac, systolic computation dblp
Sanjeev Kumar	Computer Architect Researcher Intel MRL intel.com/research/people/bios/kumar_s.htm		computer architecture, software systems dblp
H. T. Kung	Professor Harvard U eecs.harvard.edu/~htk		networking, systolic arrays, parallel computing dblp
Fadi J. Kurdahi	Professor UC Irvine eng.uci.edu/faculty/kurdahi/fadi.html		high-level synthesis, estimation and design methodology of large scale systems dblp
Jeffrey Kuskin	Atheros Communications www-flash.stanford.edu/~jsk (old)		Stanford FLASH multiprocessor dblp
Bradley C. Kuszmaul	Senior Research Scientist Supercomputing Technologies Group MIT bradley.csail.mit.edu/~bradley		CM-5, Ultrascalar, computer chess (StarTech and *Socrates), Cilk dblp