Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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David A. Padua	Professor U of Illinois Urbana-Champaign, CS polaris.cs.uiuc.edu/~padua		computer architecture and systems, parallel computing, POLARIS dblp
Yunheung Paek	Professor Seoul National U ECE, Korea compiler.snu.ac.kr		rapid ASIP prototyping, compiler optimizations for network processors, automatic parallelization PC clusters dblp
Ian Page	Reader Oxford U, UK doc.ic.ac.uk/~ipage		Handel-C, hardware compilation dblp
Vijay S. Pai	Professor Purdue U, ECE dynamo.ecn.purdue.edu/~vpai/		multiprocessors, high-performance system architecture dblp
Subbarao Palacharla	Desktop Platforms Group, Intel Corporation		complexity-effective superscalar dblp
Krishna V. Palem	Professor Georgia Tech U, ECE ece.gatech.edu/faculty/fac_profiles/bio.php?empno=504573		adaptive hardware, compiler optimizations for ILP, embedded and fault-tolerant systems, parallel computing, programmable memory hierarchies, smart caches, real-time systems, string and pattern matching, Trimaran dblp
Jens Palsberg	Professor UC Los Angeles, CS cs.ucla.edu/~palsberg		type inference for object-oriented software, interoperability of software systems, high assurance for embedded software, type-based analysis and applications dblp
David Z. Pan	Professor U of Texas at Austin ECE ece.utexas.edu/~dpan		VLSI CAD, physical design, low power, design for manufacturability dblp
Dhabaleswar K. Panda	Professor Ohio State U cis.ohio-state.edu/~panda		parallel computer architecture, wormhole routing, interprocessor communication, DSM, HPC, clustered and heterogeneous systems, quality of service, resource management dblp
Santosh Pande	Professor Georgia Tech U, CS cc.gatech.edu/~santosh		compiler optimizations for embedded and configurable systems dblp
Greg Papadopoulos	vice president, CTO Sun sun.com/aboutsun/media/ceo/mgt_papadopoulos.html		scalable systems, multithreaded/dataflow processor architecture, functional and declarative languages, fault-tolerant computing dblp
Efstathios Papaefstathiou	Microsoft Research, Cambridge, UK research.microsoft.com/users/efp		analytical and hybrid performance modeling methodologies and tools, parallel programming paradigms and development tools, software performance engineering, Indy dblp
Marios C. Papaefthymiou	Professor U of Michigan eecs.umich.edu/~marios		computer system design, energy and timing, parallel and distributed computing dblp
Corina S. Pasareanu	NASA Ames ase.arc.nasa.gov/people/pcorina		formal software verification, program abstraction, modular reasoning dblp
Nikolaos P. Paschalidis	Space Department, John Hopkins U		analog digital microlectronics, sensors and microsystems for space instruments and spacecraft avionics, space physics
Janak H. Patel	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?jhpatel		computer architecture, testing and fault-tolerance dblp
Sanjay J. Patel	Professor U of Illinois Urbana-Champaign, ECE crhc.uiuc.edu/~sjp		processor microarchitcture, computer architecture, high performance, reliable computer systems, trace cache dblp
Yale N. Patt	Professor U of Texas, Austin, ECE ece.utexas.edu/~patt Eckert-Mauchly (1996) award		HPS, two-level branch prediction, computer architecture dblp
David A. Patterson	Professor UC Berkeley, CS cs.berkeley.edu/~pattrsn von Neumann Medal (2000)		RISC, RAID dblp
Donald O. Pederson	(deceased) UC Berkeley berkeley.edu/news/media/releases/2005/01/05_donpederson.shtml		SPICE dblp
Li-Shiuan Peh	Professor Princeton U, EE ee.princeton.edu/~peh		interconnection networks dblp
Doron A. Peled	Professor University of Warwick, UK dcs.warwick.ac.uk/~doron		concurrency theory, formal verification, formal specification, semantics of programming languages, model checking, finite automata, software testing, temporal logics, partial order methods, traces dblp
Ronald H. Perrott	Professor Queen's University Belfast, United Kingdom cs.qub.ac.uk/~R.Perrott		Grid Computing, software engineering, design and implementation of parallel programming languages, high performance computing and support tools, Design/construction/analysis of algorithms dblp
Erez Petrank	Professor Israel Institute of Technology (Technion) cs.technion.ac.il/~erez		cryptography, garbage collection, computational complexity dblp
Frank Pfenning	Professor Carnegie Mellon U, CS cs.cmu.edu/~fp		programming languages, logic and type theory, logical frameworks, automated deduction dblp
Michael Philippsen	Professor U Erlangen-Nürnberg, Germany www2.informatik.uni-erlangen.de/~phlipp		compilers for Java dblp
Christian Piguet	head of the ultra-low-power sector Centre Suisse d'Electronique et de Microtechnique		very low-power microprocessors, low-power standard cell libraries, gated clock and low-power techniques, asynchronous design dblp
Lawrence T. Pileggi	Professor Carnegie Mellon U, ECE ece.cmu.edu/~pileggi		delay metrics, clock distribution and design, interconnects, timing analysis dblp
Keshav K. Pingali	Professor Cornell U, CS cs.cornell.edu/annual_report/pingali.htm		High Performance Computing, compilers, program analysis dblp
Timothy M. Pinkston	Professor U of Southern California usc.edu/dept/ceng/pinkston/people/pinkston.html		high-performance interconnection networks for multiprocessors, performance analysis, optical interconnection networks, parallel processing dblp
Nikos P. Pitsianis	Professor Duke U, CS cs.duke.edu/~nikos		numerical linear algebra and parallelization, symbolic and compiler optimization, FFTs, wavelets, simulation, high performance and scientific computing dblp
Marco Platzner	Professor ETH Zurich, Switzerland tik.ee.ethz.ch/~platzner		reconfigurable computing, hardware/software codesign, embedded systems dblp
Andrew R. Pleszkun	Professor U of Colorado, ECE ece-www.colorado.edu/faculty/pleszkun.html		computer architecture dblp
Dionisios N. Pnevmatikatos	Professor Technical U of Crete, Grece ics.forth.gr/~pnevmati		VLSI design and implementation of processors and network switches, ILP processor architectures: instruction fetching/predicated execution/compilation techniques, systems design: memory/disk/clusters of workstations dblp
Amir Pnueli	Professor Weizmann Institute, Israel wisdom.weizmann.ac.il/~amir Turing (1996) award		formal verification dblp
Fred J. Pollack	Director Intel Microprocessor Research Labs developer.intel.com/pressroom/kits/bios/fpollack.htm		Pentium Pro, i960, operating systems dblp
Constantine D. Polychronopoulos	Professor U of Illinois at Urbana-Champaign, ECE ece.uiuc.edu/faculty/faculty.asp?cdp		compilers and operating systems, parallel and distributed computing, wireless networks and mobile computing dblp
Dmitry V. Ponomarev	Professor U of Binghampton CS cs.binghamton.edu/~dima/		energy efficient design, high-end microprocessors dblp
Viktor Prasanna	Professor U of Southern California ceng.usc.edu/~prasanna		high performance computing, parallel and distributed systems, network computing, embedded systems dblp
Ian A. Pratt	Senior lecturer U of Cambridge Computer Laboratory, UK cl.cam.ac.uk/users/iap10		computer architecture, networking, operating systems, Xen dblp
Milos Prvulovic	Professor Georgia Tech, CS cc.gatech.edu/~milos		computer architecture, architectural support for programmability and productivity, fault tolerance and recovery, thread-level speculation dblp
William Pugh	Professor U of Maryland, CS cs.umd.edu/~pugh		skip lists, Omega test, algorithms and data structures, automatic parallelization, dependence analysis, Java dblp