Researchers in Computer Architecture and Compilers

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Name	Address	Picture	Work
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Ole-Johan Dahl	(deceased) Oslo U, Norway ifi.uio.no/~olejohan Turing (2001) award, von Neumann Medal (2001)		Simula, type theory, object-oriented programming dblp
Fredrik Dahlgren	Professor Chalmers U, Goteborg, Sweden ce.chalmers.se/~dahlgren		high-performance multiprocessors, multiprocessors for telecom systems dblp
William J. Dally	Professor Stanford U csl.stanford.edu/~billd Maurice Wilkes (2000) award		Imagine, J-machine, the reliable router, high-speed interconnection networks dblp
Marco Danelutto	Professor U of Pisa, Italy di.unipi.it/~marcod		parallel programming with skeletons, P3L, parallel functional, ocamlp3l, (massively) parallel architectures, ILP, Linux clusters dblp
Alain Darte	Researcher CNRS ens-lyon.fr/~darte/index-us.html		automatic parallelization, HPF, Nestor, scheduling, systolic arrays dblp
Chitaranjan R. Das	Professor Pennsylvania State U cse.psu.edu/~das		computer architecture, parallel and distributed computing, design and analysis of routing algorithms, processor management in multiprocessors, performance evaluation and fault-tolerant computing dblp
Manuvir Das	Microsoft Research research.microsoft.com/users/Manuvir/homepage.html		static program analysis, application to compilers/error detection/program verification dblp
Aravind Dasu	Professor Utah State U ece.usu.edu/ece/faculty_staff/profile.php?id=229		reconfigurable computing for media and scientific computing dblp
Edward S. Davidson	Professor (emeritus) U of Michigan eecs.umich.edu/~davidson Eckert-Mauchly (2000) award		computer architecture, supercomputing, parallel and pipelined computers, performance modeling and optimization, application code, assessment and tuning, VLSI systems, memory organization and management, CAD dblp
Jack W. Davidson	Professor U of Virginia, CS cs.virginia.edu/~jwd		zephyr, high-performance embedded applications, dynamic optimization for power dblp
Al Davis	Professor U of Utah, CS cs.utah.edu/~ald		parallel computer architecture, adaptive memory systems, asynchronous circuits and systems dblp
Nathaniel J. Davis	Professor Virginia Tech, EE ecpe.vt.edu/faculty/davisnj.html		advanced computer architectures, parallel processing, interconnection networks, computer networks, computer system simulation and performance modeling, embedded microprocessor systems dblp
Koen De Bosschere	Professor Ghent U, Belgium elis.ugent.be/~kdb		debugging of parallel programs, Java technology, link-time optimization, computer architecture dblp
Bjorn De Sutter	postdoc Gent U, Belgium elis.ugent.be/~brdsutte		binary rewriting, embedded software optimization, low-power optimization, reconfigurable computing, software protection techniques, computer architecture, program compaction dblp
Alexander G. Dean	Professor North Carolina State U cesr.ncsu.edu/agdean		computer architecture and compilation techniques for embedded systems, software thread integration dblp
Saumya K. Debray	Professor U of Arizona cs.arizona.edu/people/debray		programming languages and compilers, binary rewriting and link-time code optimization, code compression dblp
James C. Dehnert	Transmeta		compilers, Standard Template Library, Cydra 5 dblp
André DeHon	Professor Caltech U, CS cs.caltech.edu/~andre		reconfigurable hardware, DPGA, MATRIX dblp
José G. Delgado-Frias	Professor Washington State U eecs.wsu.edu/~jdelgado		VLSI microarchitectures, routers, immunity-/genetic-/neural network-based computing dblp
Robert DeLine	Microsoft Research research.microsoft.com/users/rdeline		user interfaces, software engineering, type theory, Vault dblp
James Demmel	Professor UC Berkeley, CS cs.berkeley.edu/~demmel		LAPACK, ScaLAPACK, linear systems, numerical methods dblp
Jack B. Dennis	Professor (emeritus) MIT lcs.mit.edu/people/bioprint.php3?Record_ID=26 Eckert-Mauchly (1984) award		dataflow computers, stream processors dblp
Alvin M. Despain	Professor U of Southern California isi.edu/acal/people/despain.html		computer architecture, multiprocessor systems, logic programming, quantum computation, design automation dblp
Dave Detlefs	Sun Labs East research.sun.com/people/detlefs		Extended Static Checker, Simplify theorem prover, garbage collection dblp
Srinivas Devadas	Professor MIT glenfiddich.lcs.mit.edu/~devadas		VLSI design, CAD, computer architecture, hardware validation, architectural synthesis for programmable processors, smart caches, security problems in pervasive computing dblp
Keith Diefendorff	Apple		Apple/PowerPC, AMD K6, Motorola 88110 dblp
Oliver Frank Diessel	Lecturer U of New South Wales, Sydney, Australia cse.unsw.edu.au/~odiessel		design and management of reconfigurable computer systems and applications dblp
Henry G. (Hank) Dietz	Professor U of Kentucky aggregate.org/hankd		parallel processing, compilers, hardware architectures and networking, operating systems, digital imaging dblp
Edsger Wybe Dijkstra	(deceased) U of Texas, Austin, CS cs.utexas.edu/users/UTCS/report/1997/dijkstra.html Turing (1972) award		formal methods dblp
David L. Dill	Professor Stanford U verify.stanford.edu/dill		hardware verification dblp
Chen Ding	Professor U of Rochester, CS cs.rochester.edu/u/cding		compiler enhancement of global cache reuse, dynamic program analysis and transformation, Smooth, performance tuning and prediction for memory hierarchy dblp
Pedro Diniz	Professor U of Southern California Information Sciences Institute isi.edu/~pedro		commutativity analysis, parallelizing compilers, program analysis, parallel and distributed computing, configurable computing dblp
Stephen W. Director	Dean, College of Engineering U of Michigan engin.umich.edu/director		design process, statistical VLSI design dblp
David R. Ditzel	CTO Transmeta Corp.		SPARC, Transmeta dblp
Amer Diwan	Professor U of Colorado, Boulder, CS cs.colorado.edu/~diwan		compiler analyses and optimizations, memory management, memory system performance, power-aware computing, software engineering/visualization tools dblp
Alex Doboli	Professor State U of New York at Stony Brook ece.sunysb.edu/~adoboli		CAD for embedded systems and Systems-on-Chip, specification/modeling/synthesis of heterogeneous-domain systems dblp
Apostolos Dollas	Professor Technical U of Crete mhl.tuc.gr/PERSONEL/cvs/Dollas_alt2.html		rapid system prototyping, computer architecture, reconfigurable computing, embedded systems, application specific high-performance digital systems dblp
Lorenzo Donatiello	Professor U of Bologna, Italy cs.unibo.it/~donat		performance models of computer and communication systems, performability models of fault-tolerant systems, wireless networks, parallel and distributed simulation dblp
Jack Dongarra	Professor U of Tennessee netlib.org/utk/people/JackDongarra		numerical algorithms in linear algebra, parallel computing, use of advanced-computer architectures, programming methodology and tools for parallel computers, LINPACK, MPI, PVM, ScaLAPACK dblp
José Duato	Professor Technical U of Valencia, Spain gap.upv.es/people/jduato/english.html		multicomputer systems, interconnection networks, parallel algorithms, simulation dblp
Pradeep Dubey	Intel Research intel.com/research/people/bios/dubey_p.htm		Altivec, 80386/80486/Pentium, computer architecture, multithreading, multimedia processing dblp
Michel Dubois	Professor U of Southern California, EE usc.edu/dept/ceng/dubois/dubois.html		multiprocessor architecture/performance/algorithms, rapid prototyping engine for multiprocessors (RPM) dblp
Evelyn Duesterwald	IBM		interprocedural data flow analyses dblp
Carole Dulong	co-manager, IA-64 compiler group Intel		MMX, IA-64 compilation dblp
Nikil Dutt	Professor UC Irvine cecs.uci.edu/~dutt		embedded systems design automation dblp
Shantanu Dutt	Professor U of Illinois at Chicago, ECE ece.uic.edu/~dutt		parallel and distributed computing, place and route, fault-tolerant circuits, multicomputer architecture dblp
Robert W. Dutton	Professor Stanford U, EE www-tcad.stanford.edu/tcad/bios/dutton.html		MEMS, CAD Tools, Parascope, Pisces, Suprem dblp
Vaclav Dvorak	Professor Brno U of Technology, Czech Republic fee.vutbr.cz/~dvorak		computer architecture, parallel and distributed computing, embedded and configurable systems dblp
Sandhya Dwarkadas	Professor U of Rochester, CS cs.rochester.edu/u/sandhya		InterWeave, CASHMERE, ARCH: Architecture, Runtime, and Compiler integration for HPC, processing for low-power, InterAct dblp
Harry Dwyer	Bell Labs, Lucent cm.bell-labs.com/who/dwyer		out-of-order processors dblp
Matthew B. Dwyer	Professor Kansas State U cis.ksu.edu/~dwyer		software verification, Bandera, model checking, specification dblp