I am a PhD student in the Computer Science Department at Carnegie Mellon advised by Prof. James C. Hoe and doing research in the borad area of computer architecture as a member of the Computer Architecture Lab at Carnegie Mellon (CALCM). I am a recipient of the 2012-2013 Intel PhD Fellowship.
My research focuses on hardware acceleration, reconfigurable computing, on-chip interconnects, as well as tools and methodologies to faciliate rapid hardware design and exploration. Some of my recent work includes Nautilus, a guided genetic algorithm framework for fast automated hardware design space exploration, and DELPHI, a framework for fast and efficient characterization of RTL hardware designs, which we will be soon publicly releasing.
As part of my research I have developed CONNECT, a fast lightweight and flexible Network-on-Chip (NoC) architecture to support the communication needs of FPGA and SoC applications. The CONNECT NoC architecture embodies a set of FPGA-motivated design principles to make particularly efficient use of the FPGA substrate.
My recent work on Networks-on-Chip also includes
FIST, a set of fast, lightweight, FPGA-friendly NoC modeling techniques to replace time-consuming detailed NoC models in full-system performance simulators.
In the past I worked on the ProtoFlex project, which is part of the multi-university RAMP initiative. This work included the development of FPGA-accelerated instrumentation components to study multiprocessor cache hierarchies and branch predictors. I have also worked on the problem of memory scheduling and co-authored a paper on "Thread Cluster Memory Scheduling", a new memory scheduler that exploits differences in the memory behavior of threads to maximize system throughput and fairness (IEEE Micro 2010 Top Picks paper).