| Academic Application Material: |
| CV Research Statement Teaching Statement |
| Research Summary: |
My primary research interests are in the broad area of computer architecture
with emphasis on hardware acceleration, reconfigurable computing, and on-chip
interconnects. My research agenda is driven by the need for hardware
specialization to sustain performance in the post-Dennard power-constrained era
and the need to rethink interconnects in the wake of future Systems-on-Chip
that utilize die stacking and include reconfigurable logic. I am passionate
about teaching and deeply enjoy working with students in and out of the
classroom.
My PhD thesis is on Pandora and CONNECT. Pandora is a novel
knowledge-encapsulating IP design paradigm that aims at lowering the
barrier-to-entry for building hardware accelerators and allowing
application-experts to more easily and efficiently realize their ideas in
hardware. CONNECT is a flexible Network-on-Chip IP generator that serves as a demonstration vehicle for the
Pandora principles and is actively used by multiple researchers around the
world, who have collectively generated thousands of networks and published
numerous papers using CONNECT-generated networks.
|
| Research Links: |
| The CONNECT Network-on-Chip IP Generator and our related FPGA 2012 paper. |
| Our upcoming ISPASS 2015 paper on DELPHI, which is nominated for best paper. DELPHI is a framework for fast, easy, and efficient characterization of RTL hardware designs, which we will be soon publicly releasing. |
| Our upcoming DAC 2015 paper on Nautilus, which demonstrates how IP author knowledge can be incorporated in guided genetic algorithms to vastly accelerate hardware IP design space search. |
| My work on CONNECT is also strongly tied to the CoRAM FPGA memory abstraction, which
relies on CONNECT-generated interconnects. Our
recent FCCM paper on Shrinkwrap demonstrates the potential of application-specific interconnect tuning within CoRAM. |
