Michael K. Papamichael        



I have graduated and joined Microsoft Research.

I am a PhD student in the Computer Science Department at Carnegie Mellon advised by Prof. James C. Hoe and doing research in the borad area of computer architecture as a member of the Computer Architecture Lab at Carnegie Mellon (CALCM). I am a recipient of the 2012-2013 Intel PhD Fellowship.

My research focuses on hardware acceleration, reconfigurable computing, on-chip interconnects, as well as tools and methodologies to faciliate rapid hardware design and exploration. Some of my recent work includes Nautilus, a guided genetic algorithm framework for fast automated hardware design space exploration, and DELPHI, a framework for fast and efficient characterization of RTL hardware designs, which we will be soon publicly releasing.

As part of my research I have developed CONNECT, a fast lightweight and flexible NoC architecture to support the communication needs of current and future FPGA and SoC applications. The CONNECT NoC architecture embodies a set of FPGA-motivated design principles to make the most efficient use of the FPGA substrate.

In an effort to create a useful research tool for the community, in March 2012 we publicly released CONNECT in the form of a flexible user-friendly web-based NoC generator that supports a variety of common network topologies, as well as custom user-configured networks that can be created through a visual network editor.

Since its release, CONNECT has been actively used by multiple researchers around the world, who have collectively generated thousands of networks and published numerous papers using CONNECT. My work on CONNECT is also strongly tied to the CoRAM FPGA memory abstraction, which relies on CONNECT-generated interconnects. Our work on Shrinkwrap demonstrates the potential of application-specific interconnect tuning within CoRAM.

My recent work on Networks-on-Chip also includes FIST, a set of fast, lightweight, FPGA-friendly NoC modeling techniques to replace time-consuming detailed NoC models in full-system performance simulators. In the past I worked on the ProtoFlex project, which is part of the multi-university RAMP initiative. This work included the development of FPGA-accelerated instrumentation components to study multiprocessor cache hierarchies and branch predictors. I have also worked on the problem of memory scheduling and co-authored a paper on "Thread Cluster Memory Scheduling", a new memory scheduler that exploits differences in the memory behavior of threads to maximize system throughput and fairness (IEEE Micro 2010 Top Picks paper).

In 2011, I participated in the Memocode Hardware/Software Codesign Contest, which pertained to the development of a fast simulator for a diverse class of NoCs. My FPGA-based submission, detailed in this invited MEMOCODE 2011 paper, won the first place in the "Absolute Performance" category.

While at CMU I have collaborated with various students and faculty, including Eric Chung, Yoongu Kim, Prof. Ken Mai, Prof. Babak Falsafi, and Prof. Onur Mutlu. During my 2010 internship at Intel Labs, I worked with Graham Schelle and Hong Wang in the Microarchitecture Research Lab (MRL) on uncore modeling for future multi-core systems.

I am currently serving as the Computer Science Department Graduate Student Ombudsperson. The best way to contact me is via email at .

The wordle below gives a visual summary of my research:

News & Updates

April 3, 2015
Our work on DELPHI received the ISPASS 2015 best paper award!
February 9, 2015
Our paper "Nautilus: Fast Automated IP Design Space Search Using Guided Genetic Algorithms" will appear at DAC 2015.
January 20, 2015
The DELPHI framework for fast RTL characterization (power, area, timing) will be soon publicly released. If you are interested in a pre-release version, please get in touch.
Decemer 8, 2014
Our paper "DELPHI: A Framework for RTL-Based Architecture Design Evaluation Using DSENT Models" will appear at ISPASS 2015.
April 23, 2014
New version of CONNECT is out!
March 24, 2014
Gave a guest lecture on "Interconnection Networks" for the 15-418 "Parallel Computer Architecture and Programming" course.
March 4, 2013
Our paper "ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects" will appear at FCCM 2013.
January 18, 2013
We will be holding a tutorial on CoRAM and CONNECT at FPGA 2013 on Feb. 11.
December 2, 2012
New version of CONNECT including many new features released. Check it out!
November 15, 2012
We will be holding a tutorial on CoRAM and CONNECT at MICRO-45 on Dec. 2.
October 19, 2012
Will be giving a CALCM seminar about CONNECT on Oct 30.
August 15, 2012
I was awarded the Intel PhD Fellowship for 2012-2013!
June 4, 2012
Will be giving a talk on CONNECT's fast flexible FPGA-tuned Networks-on-Chip at CARL 2012.
February 23, 2012
CONNECT, our FPGA-tuned NoC generator, was just released. Click here to try it out!
January 5, 2012
Our paper "CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs" will appear in FPGA 2012!
December 22, 2012
Our paper "Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing" will appear in FPGA 2012!
June 1, 2011
My submission to the MEMOCODE 2011 Design Contest won the first place in the Absolute Performance category!
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