I am a PhD student in the Computer Science Department at Carnegie Mellon advised by Prof. James C. Hoe and doing research in the area of Computer Architecture as a member of the Computer Architecture Lab at Carnegie Mellon (CALCM).
Currently, my research focuses at the intersection of Networks-on-Chip (NoCs) and reconfigurable computing, particularly in the form of FPGAs and CoRAM.
As part of my research I recently developed CONNECT, a fast lightweight and flexible NoC architecture to support the communication needs of current and future FPGA applications. The CONNECT NoC architecture embodies a set of FPGA-motivated design principles to make the most efficient use of the FPGA substrate.
My recent work on Networks-on-Chip also includes
FIST, a set of fast, lightweight, FPGA-friendly NoC modeling techniques to replace time-consuming detailed NoC models in full-system performance simulators.
In the past I worked on the ProtoFlex project, which is part of the multi-university RAMP initiative. This work included the development of FPGA-accelerated instrumentation components to study multiprocessor cache hierarchies and branch predictors. I have also worked on the problem of memory scheduling and co-authored a paper on "Thread Cluster Memory Scheduling", a new memory scheduler that exploits differences in the memory behavior of threads to maximize system throughput and fairness (IEEE Micro 2010 Top Picks paper).