I am a PhD student in the Computer Science Department at Carnegie Mellon advised by Prof. James C. Hoe and doing research in the area of Computer Architecture as a member of the Computer Architecture Lab at Carnegie Mellon (CALCM).
Currently, my research focuses at the intersection of Networks-on-Chip (NoCs) and reconfigurable computing, particularly in the form of FPGAs and CoRAM. Our recent work includes
FIST, a set of fast, lightweight, FPGA-friendly NoC modeling techniques to replace time-consuming detailed NoC models in full-system performance simulators.
In the past I worked on the ProtoFlex project, which is part of the multi-university RAMP initiative. This work included the development of FPGA-accelerated instrumentation components to study multiprocessor cache hierarchies and branch predictors. I have also worked on the problem of memory scheduling and co-authored a paper on "Thread Cluster Memory Scheduling", a new memory scheduler that exploits differences in the memory behavior of threads to maximize system throughput and fairness (IEEE Micro 2010 Top Picks paper).
In 2011, I participated in the Memocode Hardware/Software Codesign Contest, which required the development of a fast simulator for a diverse class of NoCs. Our FPGA-based submission, detailed in this invited MEMOCODE 2011 paper, won the first place in the "Absolute Performance" category.
While at CMU I have collaborated with various students and faculty, including Eric Chung, Yoongu Kim, Prof. Ken Mai, Prof. Babak Falsafi, and Prof. Onur Mutlu. During my 2010 internship at Intel Labs, I worked with Graham Schelle and Hong Wang in the Microarchitecture Research Lab (MRL) on uncore modeling for future multi-core systems.
The wordle below gives a visual summary of my research:
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News & Updates
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February 23, 2012
CONNECT, our FPGA-tuned NoC generator, was just released. Click here to try it out! |
January 5, 2012
Our paper "CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs" will appear in FPGA 2012! |
December 22, 2012
Our paper "Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing" will appear in FPGA 2012! |
June 1, 2011
My submission to the MEMOCODE 2011 Design Contest won the first place in the Absolute Performance category! |
March 21, 2011
Our paper "FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations" will appear in NOCS 2011! |
November 17, 2010
We will be presenting a tutorial on SimFlex & ProtoFlex at IISWC 2010 in Atlanta, GA, Dec 2-4. |
October 25, 2010
Our paper "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior" was accepted for inclusion in the IEEE Micro Top Picks January/February 2011 Issue! |
View All News & Updates
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