I am a PhD student in the Computer Science Department at Carnegie Mellon advised by Prof. James C. Hoe and doing research in the area of Computer Architecture as a member of the Computer Architecture Lab at Carnegie Mellon (CALCM).
Currently, my research focuses at the intersection of Networks-on-Chip (NoCs) and reconfigurable computing, particularly in the form of FPGAs and CoRAM.
As part of my research I recently developed CONNECT, a fast lightweight and flexible NoC architecture to support the communication needs of current and future FPGA applications. The CONNECT NoC architecture embodies a set of FPGA-motivated design principles to make the most efficient use of the FPGA substrate.
In an effort to create a useful research tool for the community, in March 2012 we publicly released CONNECT in the form of a flexible user-friendly web-based NoC generator that supports a variety of common network topologies, as well as custom user-configured networks that can be created through a visual network editor.
My recent work on Networks-on-Chip also includes
FIST, a set of fast, lightweight, FPGA-friendly NoC modeling techniques to replace time-consuming detailed NoC models in full-system performance simulators.
In the past I worked on the ProtoFlex project, which is part of the multi-university RAMP initiative. This work included the development of FPGA-accelerated instrumentation components to study multiprocessor cache hierarchies and branch predictors. I have also worked on the problem of memory scheduling and co-authored a paper on "Thread Cluster Memory Scheduling", a new memory scheduler that exploits differences in the memory behavior of threads to maximize system throughput and fairness (IEEE Micro 2010 Top Picks paper).
In 2011, I participated in the Memocode Hardware/Software Codesign Contest, which required the development of a fast simulator for a diverse class of NoCs. Our FPGA-based submission, detailed in this invited MEMOCODE 2011 paper, won the first place in the "Absolute Performance" category.
While at CMU I have collaborated with various students and faculty, including Eric Chung, Yoongu Kim, Prof. Ken Mai, Prof. Babak Falsafi, and Prof. Onur Mutlu. During my 2010 internship at Intel Labs, I worked with Graham Schelle and Hong Wang in the Microarchitecture Research Lab (MRL) on uncore modeling for future multi-core systems.
The wordle below gives a visual summary of my research:
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News & Updates
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March 4, 2012
Our paper "ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects" will appear at FCCM 2013. |
January 18, 2012
We will be holding a tutorial on CoRAM and CONNECT at FPGA 2013 on Feb. 11. |
January 18, 2012
We will be holding a tutorial on CoRAM and CONNECT at FPGA 2013 on Feb. 11. |
December 2, 2012
New version of CONNECT including many new features released. Check it out! |
November 15, 2012
We will be holding a tutorial on CoRAM and CONNECT at MICRO-45 on Dec. 2. |
October 19, 2012
Will be giving a CALCM seminar about CONNECT on Oct 30. |
August 15, 2012
I was awarded the Intel PhD Fellowship for 2012-2013! |
June 4, 2012
Will be giving a talk on CONNECT's fast flexible FPGA-tuned Networks-on-Chip at CARL 2012. |
February 23, 2012
CONNECT, our FPGA-tuned NoC generator, was just released. Click here to try it out! |
January 5, 2012
Our paper "CONNECT: Re-Examining Conventional Wisdom for Designing NoCs in the Context of FPGAs" will appear in FPGA 2012! |
December 22, 2012
Our paper "Prototype and Evaluation of the CoRAM Memory Architecture for FPGA-Based Computing" will appear in FPGA 2012! |
June 1, 2011
My submission to the MEMOCODE 2011 Design Contest won the first place in the Absolute Performance category! |
View All News & Updates
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