Outline:

1. Introduction
2. Tool Flow and Setup
3. Multiplier HDL and Test Harness
4. Redesigning the 2-operand Multiplier
5. Designing a Constant Multiplier
6. What you should handin

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1. Introduction:

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2. Tool Flow and Setup:

1. To spread the compute load.
2. To vary the results obtained.
3. To allow people to do as much as possible on their own machine, if they have one.

The Bottom Line: If you're new to this, and you don't have an AIX box on your desk, we recommend the Solaris tools for synthesis and physical design. You should be able to swap back and forth between platforms. Both Synopsys and Symplify accept VHDL and Verilog, both Xilinx tools should accept the Xilinx Netlist Format (XNF) files that are output from both synthesis tools. This SHOULD work, but in preparing this assignment we only tested the interface between the tools on one platform. You're on your own if you play on both platforms.

To set yourself up for the two platforms, we've developed two shell scripts that should set your paths and environmental variables correctly to run all these programs. Save these scripts from your browswer into your home directory.

For Solaris Machines:
setvar847.sun4_55

For AIX Machines:
setvar847.rs_aix41

If plan to use Synopsys, copy the following file to your working directory:
.synopsys_dc.setup

Everytime that you start working, you should source the setvar file by typing

% source setvar847.`sys`

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3. Multiplier HDL and Test Harness

A. Simulation: Circuit under test and test harness.

Verilog:

harness.v
mult1.v

Mult_VHDL.tar.gz

The interface between the Harness and Mult1 is simple. Mult1 has four inputs: a and b, which are twelve-bits; valid, which is a single bit indicating (when it is one) that the operands a and b are valid; and clk, which is the clock for the design. Mult1 has one output: c, which is the 24-bit product of a and b. Harness drives all the inputs of Mult1, therefore it has four outputs, and receives the single input from Mult1.

The harness has two parameters: latency and period. Latency describes how long it takes the design to output a result of a multiplication, and period describes how often, in clock cycles, the multiplier can be expected to accept operands. Mult1 has a period of one and a latency of four. In general every "period" cycles, the harness asserts valid, indicating that the multiplier should multiply the values that are on the a and b pins. "Latency" cycles later, Harness makes sure that the values coming out of the multiplier on the c bus equal the product of those previous a and b values. Note that if latency is greater than period, there are multiple multiplications going on in the multiplier at the same time. For now, you don't have to modify the values of latency and period, but you will later in the lab.

The Mult1 file describes a multiply circuit with a latency of four. This latency is implemented by having four cascaded registers that delay the product. The multiplication is described using the (*) operator.

Running the simulator:

For Verilog

For VHDL

Questions:

1. Currently, the multiplication takes place in the same cycle that the inputs are received. Rewrite this module so that the multiplication happens on the second cycle after operands arrive. What effect should this modification have on the maximum clock speed of the implementation? Will it have any effect on the size of the implementation?
2. Blocking and non-blocking assignments (answer only if you used Verilog): Change all the procedural assignments in the multiplier module to blocking ones (use the = operator rather than the <=). Why doesn't the simulation work? Can you re-write this description so that it works with blocking assignments? (Hint: no new code is needed.) Are there any risks to creating descriptions in this way? (See the on-line documentation for a discussion on non-blocking assignment.)

What you should hand in:

1. The postscript of the simwave output in simwave.ps
2. Answers to question 1 in written.txt  (head your answer as part 3A.1)
3. Answers to question 2 in written.txt (head you answers as part 3A.2)
4. A copy of the verilog using blocking assignment in the file mult2.v

B. Synthesis:

More detailed instructions for synthesis depend on the tool you are using.

Instructions for Synplify
Instructions for Synopsys
 

What you should hand in:

C. Xilinx Physical Design:

Instructions for dsgnmgr

Instructions for xmake and XDM
 

What you should hand in:

1. In written.txt as part 3C, report the number of FMAPs, HMAPs, Packed CLBs, registers, and the length of the critical path in nanoseconds.
2. Extra credit: Resynthesize, place and route the description you wrote for question one. How fast and big is the new design?  (Call this file mult3.v and place answers in written.txt as part 3C-extra).

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4. Redesigning the Two-Operand Multiplier

Suggestions:

• Highly pipelined array multiplier: In both synthesis tools, the + operator uses the fast carry logic present in Xilinx FPGAs. Build an array multiplier using a set of adders. You may want to experiment with the width of the adders that you use (12 bit adders might not be optimal.)
• Pipelined Wallace tree multiplier: Generate the logic for a Wallace tree multiplier and pipeline it. Use AND gates for the partial product generation, full adders for the partial product reduction, and a large adder (using the + operator) for the final adder.
• A pipelined Ferrari-Stefanelli multiplier. This uses a bigger multiplier (say 2x2) to generate partial products. Then you can use a Wallace tree reduction and final adder.
• Shift-and-add serial multiplier.
• Serial-serial multiplier.

Your Verilog or VHDL MUST run with Harness.v or Harness.vhd. The only thing you may change in Harness is the two parameters: PERIOD and LATENCY.

What you should hand in:

1. Verilog (or VHDL) description of multiplier in mult4.v.  Include as a comment the latency and frequency settings for test harness.
2. Postscript out of simwaves timing diagram in simwave2.ps
3. Describe any variations to the synthesis or P&R flow that you used in written.txt part 4. Also report the target FPGA, the number of CLBs, registers, and the length of the critical path. Basically, give us the results, plus enough information to duplicate the work that you did.
4. Turn in any software that you wrote to assist your design of this task.

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5. Designing a Constant Multiplier

Design the verilog for a multiplier for the following twelve bit constants:

3171 (binary: 1100 0110 0011)
2426 (binary: 1001 0111 1010)

You should re-write both the harness and the multiplier files, and simulate with at least 300 random vectors. Like in the last section, you determine period, latency and the targetted FPGA (as long as it is in the Xilinx 4000E family with -3 speed grade). We will again give better grades to more extreme designs in the throughput and area space. Here are implementation some suggestions:

• Use multiple adders, taking advantage of the fast-carry logic.
• Use look-up tables to create small (4-bit input) constant multipliers, and add the results up.

What you should hand in:

1. Verilog (or VHDL) description of multiplier in mult4.v. Include as a comment the latency and frequency settings for test harness.
2. Postscript out of simwaves timing diagram in simwave2.ps
3. Describe any variations to the synthesis or P&R flow that you used in written.txt part 4. Also report the target FPGA, the number of CLBs, registers, and the length of the critical path. Basically, give us the results, plus enough information to duplicate the work that you did.
4. Turn in any software that you wrote to assist your design of this task.

6. How You Should Handin Your Work