/* EXAMPLE DESIGN COMPILER STARTUP FILE - .synopsys_dc.setup */ /* FOR XC4000E PARTYPES */ search_path = { . \ /afs/ece.cmu.edu/common/local/usr/supported/xilinx/synopsys/libraries/syn \ /afs/ece.cmu.edu/common/local/usr/supported/synopsys/libraries/syn} link_library = {xprim_4013e-3.db xprim_4000e-3.db xgen_4000e.db \ xdc_4000e-3.db xio_4000e-3.db} target_library = {xprim_4013e-3.db xprim_4000e-3.db xgen_4000e.db \ xdc_4000e-3.db xio_4000e-3.db} symbol_library = xc4000.sdb define_design_lib WORK -path ./WORK define_design_lib xblox_4000 -path \ /afs/ece/usr/reconf/synopsys/lib/dw_xc4000 synthetic_library = {xblox_4000.sldb standard.sldb} /* compile_fix_multiple_port_nets = true xnfout_library_version = "2.0.0" bus_naming_style = "%s<%d>" bus_dimension_separator_style = "><" bus_inference_style = "%s<%d>" edifout_netlist_only = true edifout_power_and_ground_representation = cell edifout_power_name = "vcc" edifout_power_pin_name = "vcc" edifout_ground_name = "ground" edifout_ground_pin_name = "ground" edifout_write_properties_list = "instance_number port_location part" */