Open a New ProjectDo File/New Project. In the Input Design field, put mult1.xnf. Hit OK. (You might have to set your working directory first.) Fix Your EditorDo File/Preferences and change the editor to the editor of your choice, probably not vi :). Implement the DesignChoose Design/Implement from the menu. Hit Run. This will bring up a window called "Flow Engine", which will show the phases of design and the current status of the run. When the dialog comes up saying that it is complete, DON'T hit OK. View LogfileLook for any errors or warnings. Record the number of 4 input LUTs, 3 input LUTs, registers, and CLBs. How do these compare to the output of synplify?
You can click OK now. (all reports can be viewed from the Utilities/Report Browser)
Run Timing AnalyzerChoose Tools/Timing Analyzer from the menu. When the timing analyzer window comes up, choose Analyze/All Paths. This may take some time (that means go get a cup of coffee :). Look for the following in the output report:
- Total delay in ns.
- Delay breakdown between logic and routing.
Look at the placed and routed designChoose Tools/EPIC Design Editor from the menu. A new window, showing the whole chip will appear. With this editor you can change anything about the design, but we're going to be nice and not require you to do that. After you've had enough, quit EPIC with File/Exit. Quit dsgnmgrYou're done. Do File/Exit.