synplify Instructions

Start synplify:

% synplify&

Add the HDL files:

Hit the Add button, and select the mult1.v file and hit OK.

Choose the FPGA Target:

Choose Target/Set Device Options from the menu. In the dialog box, enter the following values:

Technology: Xilinx XC4000E

Part: XC4013E

Package: HQ240

Speed Grade: -3

Force GSR Usage: Enabled

Disable I/O Insertion: Disabled

Target M1 Place & Route: Enabled

Start the Synthesis tool:

Hit the huge RUN button. Even people with bad mouse skills can use this tool! The message on the right should indicate the different phases of the synthesis process.

Check out the log files:

Hit the View Log button. Look through the file for any errors or warnings. There should be one warning generated because the valid input is unused in the design. Ignore this warning. Look for the following results:

Estimated Frequency and Period:

FMAPs: (The 4-LUTs in a CLB)

HMAPs: (The 3-LUTs in a CLB)

Total packed CLBs:

Quit

The output file should be automatically saved in Mult1.xnf. So you should be able to quit, without saving the "project". Do File->Exit..

If you can't get a license read this.