Leapfrog VHDL Simulation Instructions

  1. At the unix prompt in your working directory, type:


  2. When the GUI comes up, you can double click on any of the files to look at them. When you're ready to simulate, type the following in the Text Interaction Area (the bottom-most frame):

    source run_me

  3. A new window will appear, showing the beginning of the EXERCISE procedure in Harness.vhd. Do NOT hit Run yet. First set up the trace so that you can see the waveforms display by selecting the the a variable in the top window and pressing the Wave Trace button. This should bring up the simwave window with a set up to appear as a waveform. Follow the same procedure for: b, c, valid, and clk.

  4. Now hit the Run button. The simulation should "succeed" with the seemingly contradictory message:
    ASSERT/FAILURE (time 10 US) from :$PROCESS_002 (design unit MULT1.HARNESS:EXERCISE)

    Successful Test Completion

    This is the right way for it to end. We used an assertion statement, which checks that certain conditions are being met, to exit the simulation. If there is a true assert/failure, the message you receive will not as nice as "Successful Test Completion."
  5. In order to look at the waveform display, Do View/Zoom Out a couple of times in the simwaves menu. Set the display so that you can see the first ten cycles or so. The rising edge of valid must be visible in the left portion of the screen.

  6. File/Print/Single Page... Generate a PostScript file of the current view. Print this out and turn it in.

  7. To exit the simulation, select Quit or Exit from the menus of each of the tools that are currently running.

If you can't get a license read this.