/*
 *  File: Mult1.v
 *  Module: multiplier
 *  Author: Herman Schmit
 *  Date: Dec 22, 1997
 *  
 *  Purpose:
 *  Declare a multiplier with a period of one and latency of four.
 *  Uses the built-in * operator to describe a multiplication.
 *
 *  The ONLY reason this implementation has four registers and the 
 *  four cycle latency is to demonstrate the use of the test harness
 *  for multipliers with latency.  The multiplier operands, a and b, 
 *  are read directly from unregistered input pins.
 */

module multiplier (a,b,valid,c,clk);
   input [11:0] a,b;
   input valid;
   output [23:0] c;
   input clk;
   
   reg [23:0] c1, c2, c3, c;

   always @(posedge clk)
    begin
       c1 <= a * b;
       c2 <= c1;
       c3 <= c2;
       c  <= c3;
    end
   
endmodule /* multiplier */