CS-740 Project Report
Exploring different L2 cache designs for reducing cache misses
Amit Kr. Manjhi & Susmit Sarkar
Dec 3, 2001
The memory latency is becoming a serious bottleneck in the performance of computer
systems. This suggests that a careful study of cache parameters and cache management strategies is
needed to find ways of alleviating this problem.
In this study, we simulate and evaluate different history-based cache management strategies for a L2 data cache.
We test some novel schemes designed to leverage the common data access patterns in real-world programs.
Our evaluation method is simple and only takes into account the number of
cache misses. We quantify how the cache miss rates are impacted by
varying cache parameters. Finally, we also explain a surprise finding of our
Amit K Manjhi