Scribe Notes
Logic Emulation Technology

By Mihai Budiu
Reconfigurable Computing Seminar 2/18/98
Slide 1 Slide 1: Logic Emulation Technology

Slide 2 Slide 2: Background
The IC simulation may be the only application.
Quickturn systems were started 7--8 years ago.












	    ^
          yrs  silicon
design	    |     
turnaround  |	     logic
      	    |	     emulation
	    |
	    |        Teramac
         secs                   simulation     
            |
	    +-----s-----------------y----->
                  e                 r
                  c                 s

	         simulation time
                  (Boot the OS)
The problems addressed by these two papers are:
Slide 3 Slide 3: PLASMA Architecture
Plasma is a hierarchical design.
For this architecture the Rent's exponent is > 0.7.

Slide 4 Slide 4: Register Files
Muliple read ports can be easily done in FPGA, but not multiple writes.
How do they account for 40PALE/1 bit?
Slide 5 Slide 5: Teramac Architecture
Compilation at any cost.

Slide 6 Slide 6: Teramac CAD
Most impressive.
CAD parallels architecture with heirarchical decomposition. The cost of the device is not mentioned. Is this really cheaper?
The philosophy is: don't be constrained by your resources.
This is a compiler-driven architecture.
Slide 7 Slide 7: Teramac Philosophy
The question we may ask: should reconfigurable computing be farther to the right or to the left on this axis? Is there a "sweetspot"?
Perhaps the place should depend on the market.
Reconfigurable computing will not become mainstream unless compilation is fast and robust.
The fact that such a large design has many faults in the components is not addressed in this paper. At FCCM 97, HP discussed compilation around hard faults on PLASMA chips and Teramac boards. (There were 1000s of faults in these systems.)
Slide 8 Slide 8: Virtual Wires
Why are necessary the multiple phases? A combinatorial wire which spans multiple circuits needs to be evaluated in phases.

Limitations: They can't allow asynchronous or meta-stable circuits across chips. They also can't deal with multiple clocks.
In each phase only part of the logic is utilized.
This hardware virtualization is a valuable idea.
This is a precursor of the RAW machine.

Slide 9 Slide 9: Virtual Wires Philosophy
This graph depicts the fact that one uses more logic in the chip to build wires.
What's nice is that the same netlist can be used to configure this machine as for usual FPGA's.
Scribed by Mihai Budiu