file: placer.hxx



/* implements structure that holds the nets connected to 
   each gate on the chip 
*/
typedef struct gate {
   int netsOnGate;
   int *List;
} gateList;

/* implements structure that holds the gates connected to 
   each net on the chip
*/
typedef struct net {
   int GateID;
   int Type;
   struct net *next;
} netList;

/* implements structure that holds the pads connected to 
   each net on the chip
*/
typedef struct pad {
   int PadID;
   struct pad *next;
} padList;

/* implements structure holding pin location constraints
*/
typedef struct pin {
   int NetID;
   int xSite; 
   int ySite;
} pinList;

/* implements structure holding timing paths from input 
   netlist 
*/
typedef struct timing {
   int NumObjects;
   int *List;
} timingList;

// simple delay model
#define PIN_DELAY 1.0
#define GATE_DELAY 1.0

void readPinFile(FILE *PinFile);
void readNetList(FILE *File);
void printUsage();
void addToList (int Net, int Gate, int Type);
double computeWireLen(int, int);
void initNetList();
//void recursiveMinCut(int, int, int, int, int);
void recursiveMinCut(MetisIntfc, int, int, int, int, int);
void printWireLen();
void drawChip();
int getCapacity(int sx, int sy, int ex, int ey);
void fixCapacityViolations(int Partition, int Capacity1, int Capacity2);
int pickGate(int Partition, int NumGates);
void moveToPartition(int Gate, int Partition);
double getGateLen(int Gate);
void writeOutput(void);
void computeWireDelay(void);
int foundViolations ( int Partition, int, int Capacity1, int Capacity2 );
void adjustGatePosition ( int Partition, int sx, int sy, int ex, int ey );
int cutsThisPartition ( int Net, int Partition );
int getFanout ( int Net );
void quadPlace(int Partition, int sx, int sy, int ex, int ey);
void initParts(void);
void greedySwap(int Partition);
double getRatio(int Partition, int Cut);
double computeLen(int Gate1, int Gate2);
void fixQuadViolations(int PartitionNum, int sx, int sy, int ex, int ey, int Area1, int Area2, int Area3, int Area4);



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