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THE AUTHOR CAN MAKE THESE CHANGES IF HE/SHE WISHES. to the cache will require a certain number of reads, some computation, and a certain number of writes to update the data structure. Let $n_o$ be the number of instructions executed per tuple, $\gamma$ is the number of reads per tuple, and $\delta$ is the number of writes per tuple. We make the simplifying that the cache data structure is (memory) cache optimized, so that the read and write performance can be characterized with the stride-1 contiguous read and write numbers, $r_{rc}$ and $r_{wc}$, respectively. Then the time to add the elements to the cache becomes \\ $$t_o = n (n_o/r_i + \gamma/r_{rc} + \delta / r_{wc})$$ \\ In the simple address-data-pair case, $n_o\approx 0$, $\gamma=0$, and $\delta=2$. When assembling the message using the cached address relation, we model the time spent accessing the cache is being limited by the contiguous read performance of the machine. We feel this is reasonable because a final stage of the cache update time $t_o$ can always be spent converting between a data structure optimized for additions to one optimized for use during assembly. Because of this possible change of data structure, we must introduce an additional term, $\beta$, which represents the number of words read from the cache per data word. Then the time to assemble the message is \\ $$t_{ac}=n(\beta/r_{rc} + 1/r_{rr} + (1+\alpha)/r_{wc})$$ \\ Notice that this expression combines $\beta$ and $\alpha$ - the portion of the time spent reading from the cache depends on the cache data structure while the portion spent writing to the message depends on the message format. The total cached communication time for an $n$ word message is \\ $$t_{cached} = n((n_g/r_i + (n_o/r_i + \gamma/r_{rc} + \delta/r_{wc}))/n_i + \beta/r_{rc} + 1/r_{rr} + (1+\alpha)/r_wc + (1+\alpha)/r_c + (1+\alpha)/r_{rc}+ 1/r_{wr})$$ \subsection{Evaluating Caching in Light of the Extended Models} As before, we note that for an implementation with caching to ever outperform one without, it must be true that \\ $$t_{ac} < t_g + t_{au}$$ \\ means (as in section \ref{simple cache}) that \\ $$r_{rc} > \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac} \beta r_i / n_g $$ \\ or, more interestingly, that \\ $$\beta < n_g r_{rc}/r_i $$ \\ The latter expression is telling us that the representational efficiency of the cached address relation determines whether caching is effective or not. Surprisingly, the efficiency of the message format does not come into play. If caching can win, then the breakeven point is determined by setting $t_{cached}=t_{uncached}$ and solving for $n_i$, the number of times the communication is performed. We find that the break-even point is where \\ $$n_i = \lfloor ((n_g+n_o)r_{rc} + \gamma r_i + \delta r_i r_{rc}/r_{wc}) / (n_g r_{rc} - \beta r_i) \rfloor $$ \\ \section{One-to-many Communication and Caching} So far, we have developed a model to predict the average performance of a single point-to-point communication without and with caching. If the hardware does not support concurrency between actual communication (``getting it on the wire'') and computation, then determining the total time for depositing to $n_p$ processors $n_i$ times is \\ $$ n_i\sum_{i=0}^{n_p-1}t_{(pp,i)} $$ \\ where $t_{(pp,i)}$ is the point-to-point time, $t_{cached}$ or $t_{uncached}$, time for the message sent to processor $i$. This time can be optimized by choosing whichever of cached or uncached communication is best for each individual point-to-point time. If the hardware supports communication concurrently with computatation, then some complexity arises. In the following, we assume that the number of data words and the amount of computation and memory references is the same for each target processor -- that $t_{(pp,0)}=t_{pp,1)}=\dots=t_{(pp,n_p-1)}$ and the components of each of the $t_{(pp,i)}$ are equal. Because of the concurrency between the communication and computation, we assemble the message for processor $i$ while sending the message for processor $i-1$. Suppose that the time to assemble a message is less than that to send a message, then the total time spent performing the communication is overwhelmingly dominated by the communication time. Without caching, we find that the total time required is \\ $$ t_g+t_{au}+n_in_pt_c+t_d$$ \\ whereas with caching we require \\ $$ n_p(t_g+t_o) + t_{ac} + n_in_pt_c+t_d$$ \\ therefore, caching will only make sense if $t_g < (t_{au}-t_{ac})/(n_p-1)$, which is unlikely. See figure \ref{commbig}. Even if this is found to be true, caching is unlikely to be of much help. If the time to assemble a message is greater than that to send a message, then the total time to perform the communication is dominated by the assembly time. Without caching, the total time required is \\ $$ n_in_p(t_g+t_{au})+t_c+t_d $$ \\ whereas with caching the total time is \\ $$ n_p(t_g+t_o)+n_in_pt_{ac} + t_c +t_d$$ \\ In this case, caching makes sense if $t_{ac}