#
#                  I N T E L   P R O P R I E T A R Y
#
#     COPYRIGHT (c)  2003 BY  INTEL  CORPORATION.  ALL RIGHTS
#     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY
#     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A
#     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
#     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
#     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT
#     THE PRIOR WRITTEN PERMISSION OF :
#
#                        INTEL  CORPORATION
#
#                    2200 MISSION COLLEGE BLVD
#
#               SANTA  CLARA,  CALIFORNIA  95052-8119
#


#	convert \ to / in $IXA_SDK_DEV

ROOT= ${subst \,/, ${IXA_SDK_DEV}}

SRC_ROOT= ${ROOT}

PDL_DIR= ./dispatch_loop
LIST_DIR= list
UOF_DIR=.

RM= rm
MD= mkdir

DEFS_SIMULATION=	-DSIMULATION
DEFS_HARDWARE=		-DUSE_IMPORT_VAR

#	Default configuration is SIMULATION
#	Define in command line like make CONFIG=HARDWARE to change it

CONFIG?=	HARDWARE

DEFS=	${DEFS_${CONFIG}}

ASM_FLAGS= -ixp2400 -REVISION_MIN=0x01 -O -W3 -R -lm 0 -g

GLOBAL_DEF= -DIXP2400 -DIXP_MICROCODE -DIX_PLATFORM_2401 -DSRAM_CH1_NOT_PRESENT -DDISABLE_PR5_REWORK ${DEFS}


#	Directories of various source files.

ETH_IPV4_DIR= 		${PDL_DIR}
PACKET_RX_DIR=		${SRC_ROOT}/src/building_blocks/rx/microengine/packet_rx/microcode
QM_PACKET_DIR=		${SRC_ROOT}/src/building_blocks/queue_manager/qm_packet/microcode
SCHEDULER_PACKET_DIR= 	${SRC_ROOT}/src/building_blocks/scheduler/scheduler_packet/microcode
SPHY_MPHY4_TX_DIR=	${SRC_ROOT}/src/building_blocks/tx/microengine/packet_tx/sphy_mphy4/microcode

#	Include Directories

INCLUDE_DIR=    -I${SRC_ROOT}/src/include							\
		-I${PDL_DIR}									\
		-I./										\
		-I${SRC_ROOT}/src/library/dataplane_library/microcode				\
		-I${SRC_ROOT}/src/library/microblocks_library/microcode				\
		-I${SRC_ROOT}/src/library/microblocks_library/include				\
		-I${SRC_ROOT}/src/building_blocks/rx/microengine/packet_rx/microcode		\
		-I${SRC_ROOT}/src/building_blocks/rx/microengine/csix_rx/microcode		\
		-I${SRC_ROOT}/src/building_blocks/rx/microengine/l2_decap/ethernet_decap/microcode \
		-I${SRC_ROOT}/src/building_blocks/tx/microengine/ethernet_arp/microcode		\
		-I${SRC_ROOT}/src/building_blocks/ipv4/microcode				\
		-I${SRC_ROOT}/src/building_blocks/ipv4/include					\
		-I${SRC_ROOT}/src/building_blocks/queue_manager/qm_cell/microcode		\
		-I${SRC_ROOT}/src/building_blocks/scheduler/scheduler_csix/microcode		\
		-I${SRC_ROOT}/src/building_blocks/tx/microengine/csix_tx/microcode		\
		-I${SRC_ROOT}/src/building_blocks/tx/microengine/l2_encap/ethernet_encap/microcode \
		-I${SRC_ROOT}/src/building_blocks/queue_manager/qm_packet/microcode		\
		-I${SRC_ROOT}/src/building_blocks/scheduler/scheduler_packet/microcode		\
		-I${SRC_ROOT}/src/building_blocks/tx/microengine/packet_tx/sphy_mphy4/microcode


#	need to add system_init.c
ETH_IPV4_FILES= 	${ETH_IPV4_DIR}/dispatch_loop.uc		\
			${ETH_IPV4_DIR}/dl_source.uc			\
			${ETH_IPV4_DIR}/ethernet_ipv4.uc		\
			${ETH_IPV4_DIR}/pkthdr_cache.uc			\
			${ETH_IPV4_DIR}/quad_gbeth_dl_source.uc		\
			${ETH_IPV4_DIR}/quad_gbeth_system_init.uc	\
			${ETH_IPV4_DIR}/system_init.uc



PACKET_RX_FILES=	${PACKET_RX_DIR}/packet_rx_common_util.uc	\
			${PACKET_RX_DIR}/packet_rx_init.uc		\
			${PACKET_RX_DIR}/packet_rx_one_me_util.uc	\
			${PACKET_RX_DIR}/packet_rx_two_me_util.uc	\
			${PACKET_RX_DIR}/packet_rx.uc

SPHY_MPHY4_TX_FILES=	${SPHY_MPHY4_TX_DIR}/sphy_mphy4_tx_init.uc	\
			${SPHY_MPHY4_TX_DIR}/sphy_mphy4_tx.uc		\
			${SPHY_MPHY4_TX_DIR}/sphy_mphy4_tx_util.uc

QM_PACKET_FILES=	${QM_PACKET_DIR}/qm_packet_code.uc		\
			${QM_PACKET_DIR}/qm_packet_macro.uc		\
			${QM_PACKET_DIR}/qm_packet_message.uc

SCHEDULER_PACKET_FILES= ${SCHEDULER_PACKET_DIR}/scheduler_packet.uc	\
			${SCHEDULER_PACKET_DIR}/scheduler_qm.uc

LIST_FILES=			${LIST_DIR}/app_dl_a.list		\
				${LIST_DIR}/app_dl_b.list		\
				${LIST_DIR}/app_dl_d.list		\
				${LIST_DIR}/sphy_mphy4_tx.list 		\
				${LIST_DIR}/sphy_mphy4_tx_1.list	\
				${LIST_DIR}/packet_rx.list		\
				${LIST_DIR}/qm_packet.list		\
				${LIST_DIR}/scheduler_packet.list


default:: ${UOF_DIR}/quad_gbeth_2401.uof


${UOF_DIR}/quad_gbeth_2401.uof: ${LIST_FILES}

	ucld		-u 1 	-l ${LIST_DIR}/app_dl_a.list		\
			-u 2 	-l ${LIST_DIR}/app_dl_b.list		\
			-u 19 	-l ${LIST_DIR}/app_dl_d.list		\
			-u 17   -l ${LIST_DIR}/sphy_mphy4_tx.list 	\
			-u 18   -l ${LIST_DIR}/sphy_mphy4_tx_1.list	\
			-u 0 	-l ${LIST_DIR}/packet_rx.list		\
			-u 3 	-l ${LIST_DIR}/qm_packet.list		\
			-u 16 	-l ${LIST_DIR}/scheduler_packet.list	\
			-g 						\
			-sc 0x00000004:0x00003ffc 			\
			-dr 0x00000010:0x7ffffff0 			\
			-sr0 0x00000004:0x03fffffc 			\
			-sr1 0x00000004:0x03fffffc 			\
			-sr2 0x00000004:0x03fffffc 			\
			-sr3 0x00000004:0x03fffffc 			\
			-o ${UOF_DIR}/quad_gbeth_2401.uof

${LIST_DIR}/app_dl_a.list: ${ETH_IPV4_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DMICROENGINE -DMICROCODE -DCHIP_VERSION=IXP2XXX		\
		-DRFC1812_SHOULD -DMETA_CACHE_SIZE=8 -DIPV4_START_ME		\
		-DDL_NEXT_ME=0x02 -DIP_HDR_OFFSET=14 -DRFC2644_CHECKS 		\
		-DDBCAST_TABLE_BLOCK_SIZE=8 -DPROCESS_CONTROL_BLOCK 		\
		-DETHER_WITHOUT_L2 -DDISABLE_MAC_FILTERING 			\
		-o ${LIST_DIR}/app_dl_a.list 					\
		${ETH_IPV4_DIR}/ethernet_ipv4.uc

${LIST_DIR}/app_dl_b.list: ${ETH_IPV4_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DMICROENGINE -DMICROCODE -DCHIP_VERSION=IXP2XXX 		\
		-DRFC1812_SHOULD -DMETA_CACHE_SIZE=8 -DDL_NEXT_ME=0x13 		\
		-DIP_HDR_OFFSET=14 -DRFC2644_CHECKS -DDBCAST_TABLE_BLOCK_SIZE=8 \
		-DPROCESS_CONTROL_BLOCK -DETHER_WITHOUT_L2 			\
		-DDISABLE_MAC_FILTERING 					\
		-o ${LIST_DIR}/app_dl_b.list 					\
		${ETH_IPV4_DIR}/ethernet_ipv4.uc

${LIST_DIR}/app_dl_d.list: ${ETH_IPV4_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DMICROENGINE -DMICROCODE -DCHIP_VERSION=IXP2XXX 		\
		-DRFC1812_SHOULD -DMETA_CACHE_SIZE=8 -DDL_NEXT_ME=0x01 		\
		-DIP_HDR_OFFSET=14 -DRFC2644_CHECKS -DDBCAST_TABLE_BLOCK_SIZE=8 \
		-DPROCESS_CONTROL_BLOCK -DSTART_ME=0x01 -DETHER_WITHOUT_L2 	\
		-DDISABLE_MAC_FILTERING 					\
		-o ${LIST_DIR}/app_dl_d.list 					\
		${ETH_IPV4_DIR}/ethernet_ipv4.uc

${LIST_DIR}/packet_rx.list: ${PACKET_RX_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DETHER_RECEIVE -DPOS_PHY_LEVEL_3  		 		\
		-o ${LIST_DIR}/packet_rx.list 					\
		${PACKET_RX_DIR}/packet_rx.uc

${LIST_DIR}/sphy_mphy4_tx.list: ${SPHY_MPHY4_TX_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DSCHEDULER_ME=0x10 -DTHIS_ME=PACKET_TX_FIRST_ME -DETHERNET_TX 	\
		-DEGRESS -DADD_L2_HEADER 					\
		-o ${LIST_DIR}/sphy_mphy4_tx.list				\
		${SPHY_MPHY4_TX_DIR}/sphy_mphy4_tx.uc

${LIST_DIR}/sphy_mphy4_tx_1.list: ${SPHY_MPHY4_TX_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DSCHEDULER_ME=0x10 -DTHIS_ME=PACKET_TX_SECOND_ME 		\
		-DETHERNET_TX -DEGRESS -DADD_L2_HEADER 				\
		-o ${LIST_DIR}/sphy_mphy4_tx_1.list				\
		${SPHY_MPHY4_TX_DIR}/sphy_mphy4_tx.uc

${LIST_DIR}/qm_packet.list: ${QM_PACKET_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DEGRESS 				 			\
		-o ${LIST_DIR}/qm_packet.list 					\
		${QM_PACKET_DIR}/qm_packet_code.uc

${LIST_DIR}/scheduler_packet.list: ${SCHEDULER_PACKET_FILES}
	[ -d ${dir $@} ] || ${MD} ${dir $@}
	uca ${ASM_FLAGS} ${INCLUDE_DIR}						\
		${GLOBAL_DEF}							\
		-DEGRESS				 			\
		-o ${LIST_DIR}/scheduler_packet.list 				\
		${SCHEDULER_PACKET_DIR}/scheduler_packet.uc

clean::
	-${RM}	${LIST_DIR}/*.list ${LIST_DIR}/*.uci ${LIST_DIR}/*.ucp ${UOF_DIR}/*.uof 2>/dev/null	

