This is the front page for the ECE Capstone course on Network Design and Evaluation.
The goal of this course is to learn about network design and evaluation in a hands-on fashion. Teams of students will design, implement, and evaluate a network protocol or a router feature.
Each team of students will develop three interacting network components. A first component is a data plane component, i.e. a network element that is involved in processing packets that are forwarded by the router. This component will be implemented on the packet processor. Examples include a packet scheduler that supports quality of service, or packet filtering for a security firewall. The second component is a control plane component that manages and controls the function that is implemented on the packet processor. Examples could be a signaling protocol that sets up the QoS packet scheduler, or a management interface for a firewall. A third component will consist of one or more applications that stress the new network feature. For example, a video streaming application that uses a connection with a bandwidth guarantee, or an application that tries to break into a network protected by a firewall. Some example projects are described here . Teams will consist of two to four people.
In the first two weeks of the semester, teams have to complete a project proposal that identifies the team members and high-level goals of the proposed project. The proposal will be followed by a detailed project design. The design must describe the specific function that the team will implement, any existing software that the team will use, a project plan including the responsibilities of the team members and milestones, and an evaluation plan. The middle of this semester will be devoted to implementation. During this stage, we will have regular project design reviews. The last three weeks of the semester will be devoted to testing, evaluation, and writing of the final report.
The platform for the course project consists of an Intel Development platform for the IXP 2400 network processor. It is a PCI card that includes an IXP 2400 chip, memory and three gigabit Ethernet interfaces. The card functions as a small but realistic router that is highly programmable. “Network processors" such as the IXP 2400 are chips that have been developed specifically for use in the core of high speed routers and switches. Similar to the CPUs used in PCs and workstations, network processors are programmable chips, but their instruction set and memory hierarchy have been optimized to support protocol processing operations. A router based on a network processor is a very attractive platform for teaching purposes: it is a realistic, high-performance router that can be fairly easily modified
Tuesday and Thursday 3:00-4:20, Room PH A18C.
Peter Steenkiste ,
prs@cs.cmu.edu
8202 Wean Hall, x8-3261
Angela Miller, Wean Hall 8215, amiller@cs.cmu.edu
Chris Marshall, cmarshal@andrew.cmu.edu, x8-5632
Amy Lu, meihsual@andrew.cmu.edu,
x8-7114
Peter Steenkiste, Tuesday 11-noon, Wean Hall 8202
Chris Marshall, Thu 5-6 and Fri 1-2, CIC 2314F
Amy Lu, Mon 5-6 and Wed 4-5, PH B42
"IXP2400/2800 Programming: The Complete Microengine Coding Guide", Erik Johnson and Aaron Kunze, Intel Press, ISBN 097178616X. Available from online book vendors, e.g. Barnes and Noble, Amazon, ...
Projects will be take place in the lab in Hamburg Hall A016. If you are registered for the course, you will get a key that will give you access to the lab at any time.
Students must have taken at least a full-semester introductory course in data networking (e.g. 18-345 or 15-441), or they must be able to demonstrate an equivalent background. Students must also have solid programming experience in C, including experience in network programming (e.g. 15-213 or equivalent).
The following documentation is available (CMU only):
There is also a bboard available for discussion on the use of the IXP 2400:
post+academic.ece.18-544@andrew.cmu.edu
Tentative lecture schedule for Fall 06:
|
When |
What |
Where |
|
|
Tu 8/29 |
Classroom |
Chapter 2 |
|
|
Th 8/31 |
Classroom |
Chapter 4 |
|
|
Tu 9/5 |
Lab session on IXP programming |
Lab |
- |
|
Th 9/7 |
Lab session on IXP programming |
Lab |
Chapter 3 |
|
Tu 9/12 |
Classroom |
- |
|
|
Th 9/14 |
Classroom |
Required: Overview; Optional: Optical |
|
|
Tu 9/19 |
Lab |
- |
|
|
Th 9/21 |
Project discussion |
Lab |
- |
|
Tu 9/26 |
Lab session |
Lab |
- |
|
Th 9/28 |
Lab session |
Lab |
- |
|
Tu 10/3 |
Design presentations |
Classroom |
- |
|
Th 10/5 |
Design feedback - required |
Lab |
- |
|
Tu 10/10 |
Lab session – P2 demos |
Lab |
- |
|
Th 10/12 |
Lab session - required |
Lab |
- |
|
Tu 10/17 |
Lab session (optional) |
Lab |
- |
|
Th 10/19 |
Lab session (optional) |
Lab |
- |
|
Tu 10/24 |
Status feedback meetings - required |
Wean 8202 |
- |
|
Th 10/26 |
Guest lecture, Mike Benson, Netronome Systems |
Classroom |
- |
|
Tu 10/31 |
Guest lecture, Prashant Chandra, Intel |
Classroom |
- |
|
Th 11/2 |
Status presentations |
Classroom |
- |
|
Tu 11/7 |
Lab session/talk about Research Discussion |
Lab |
- |
|
Th 11/9 |
Lab session (optional) |
Lab |
- |
|
Tu 11/14 |
Classroom |
- |
|
|
Th 11/16 |
Classroom |
- |
|
|
Tu 11/21 |
Lab session |
Lab |
- |
|
Th 11/23 |
Thanksgiving - No Class |
- |
- |
|
Tu 11/28 |
Lab session |
Lab |
- |
|
Th 11/30 |
No class |
- |
- |
|
Tu 12/5 |
Project demos |
Lab |
- |
|
Th 12/7 |
Final project presentations |
Classroom |
- |
Tentative list deadlines for the course project:
|
Report |
Due Date |
|
Project topics |
Friday 9/8 |
|
Architecture block diagram (powerpoint) |
Wednesday 9/27 - 5pm |
|
Monday 10/2 - 8am |
|
|
Weekly individual status e-mails |
Every Friday, starting 9/29 |
|
Design presentation |
Tuesday 10/3 |
|
First status report |
Thursday 10/19 midnight (hard) |
|
Status presentation |
Thursday 11/2 |
|
Second status report |
Thursday 11/9 |
|
Third status report |
Wednesday 11/29 |
|
Final project demos |
Thursday 11/30 |
|
Final project presentations |
Thursday 12/7 |
|
Final reports due |
Midnight, Thursday 12/14 |
Assignment due dates:
|
Assignment |
Handed out |
Due date |
|
Thursday 9/7 |
Thursday 9/21 |
|
|
Thursday 9/21 |
Friday 10/6 |
The grade for the course is based on the quality of the course project (60%), project management (15%), the quality of the presentations (10%) and project documents (15%). The course project has three phases: design, implementation, and evaluation; all three phases contribute equally to the grade. Another factor that affects the grade on the project is the complexity of the project, relative to the size of the team. Students will be given feedback on the complexity of their project during the design phase. Students will also be given feedback on the quality of their presentations and documents so they can improve the presentations and documents throughout the semester.