I am a part of the Phoenix project, which aims
to develop techniques and methods to implement programs directly in
hardware using reconfiguration. My advisor is Seth Copen Goldstein.
My thesis research focuses on the Tartan Reconfigurable
Architecture. The two specific aspects I am looking at are in-fabric
caching to reduce memory access latency and improve performance; and
virtualization to reduce area requirements and improve the near-term
viability of the architecture.
The Tartan architecture has been designed to have low power
consumption, high performance, high tolerance for defects, and rapid
design turn-around starting from a high-level user application written
in C. This is achieved by employing coarse-grained reconfigurability,
self-scheduled execution, asynchronous circuits, redundancy and
inter-changeability in available hardware resources, and by designing
Tartan to closely match the Pegasus Intermediate Representation used
in the CASH high-level synthesis flow (see
http://www.cs.cmu.edu/\~phoenix). Currently, high-level applications
written in C can be translated into configurations for Tartan in a
matter of minutes to hours.
The major performance limitation in Tartan's current design arises
from accessing memory, including the run-time arbitration and
serialization overhead between potentially concurrent memory
operations. The first part of my thesis research focuses on
distributing the L1 cache inside the Tartan fabric, and improving the
arbitration mechanisms to reduce overhead. As part of the effort
to distribute the L1 cache, I plan to devise coherence schemes that
are suitable for Tartan's execution model.
The second part of my research focuses on making the Tartan fabric
virtualizable, to allow large programs to be executed with relatively
modest hardware requirements. As part of this effort, I am studying
strategies and heuristics to prefetch, place and evict parts of the
program configuration. This will allow Tartan to be a practical
execution substrate in the near future.
As part of my past work, I have developed testing methods and
defect-tolerance strategies that allow us to locate manufacturing
defects in a large reconfigurable fabric such as Tartan, and to
place-and-route the user application around these defects.
Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish
Venkataramani, Mihai Budiu and Seth C. Goldstein, Tartan: Evaluating
Spatial Computation for Whole Program Execution, in
Proceedings of the Twelfth International Conference on Architectural
Support for Programming Languages and Operating Systems (ASPLOS-XII),
Oct 21-25, 2006, San Jose, CA. 163-174. pdf
T Vogels, T Zanon, R Desineni, R D Blanton, W Maly, J G Brown, J E
Nelson, Y Fei, X Huang, P Gopalakrishnan, M Mishra, V Rovner and S
Tiwary, Benchmarking diagnosis algorithms with a diverse set of IC
deformations, in Proceedings of the International Test Conference,
Oct 26-28, 2004, Charlotte, NC. 508-517. pdf
Mahim Mishra and Seth C. Goldstein, Defect Tolerance at the End
of the Roadmap, in Nano, Quantum and Molecular Computing:
Implications to High Level Design and Validation, Sandeep
K. Shukla and R. Iris Bahar (Eds.), Kluwer Academic Publishers,
Boston, 2004. 73-108. publisher's site
Mahim Mishra and Seth C. Goldstein, Defect Tolerance at the End
of the Roadmap, in Proceedings of the International Test
Conference (ITC '03), Sep 30-Oct 3, 2003, Charlotte, NC. pdf
Seth Goldstein, Mihai Budiu, Mahim Mishra, and Girish
Venkataramani, Reconfigurable Computing and Electronic Nanotechnology,
invited paper in IEEE 14th International Conference on
Application-specific Systems, Architectures and Processors, June
24-26, 2003, The Hague, Netherlands. pdf
Mahim Mishra and Seth C. Goldstein, Defect Tolerance at the End
of the Roadmap, in Proceedings of the 10th International Test
Synthesis Workshop, Mar 30-Apr 2, 2003, Santa Barbara,
CA. pdf
M. Budiu, M. Mishra, A. Bharambhe, S. C. Goldstein, Peer-to-peer
Hardware-software Interfaces for Reconfigurable Fabrics, in
Proceedings of the IEEE Symposium on Field-Programmable Custom
Computing Machines 2002 (FCCM '02), Napa, CA, April 21 - 24,
2002. pdf
M. Mishra, S. C. Goldstein, Scalable Defect Tolerance for
Molecular Electronics, in Proceedings of the 1st Workshop on
Non-Silicon Computing (NSC-1), 8th International Symposium on
High-Performance Computer Architecture, Cambridge, MA, February 3,
2002. pdf
A. Mukerjee, R. Bhattacharjee, M. Mishra, HIVE: An HPSG Interface
for Video Animation, in Proceedings of the First International
Conference on Multimedia Processing and Systems, Madras, India,
August 13 - 15, 2000.