15-213 Introduction to Computer Systems
Lecture 17: Pentium/Linux Memory System

• Reading: Ch 10.7-10.8; Notes
• Slides: none
• Code: none
• Concepts:
  • x86-64 memory system
  • Linux memory management and layout
  • Linux page fault handling
  • Heap memory
• Previous lecture: Virtual Memory
• Next lecture: Dynamic Storage Allocation

Notes on Lab Machines

These are a few notes about the cache characteristics of the processor used for this class, the Intel Nocona Xeon, which is a dual 3.2 GHz IA32-EM64T processor. This information was copied from the Fall 2005 instance of this course and other Internet sources.

• 48 bits virtual address
• 36 bits physical address
• 4 KB page size
• 4-level page tables with 512 entries per table
• Data TLB with 64 entries, fully associative
• Instruction TLB with 128 entries, fully associative
• L1 instruction cache: 12KB, 8-way set associative, 64 byte blocks
  1 cycle access time for cache hit
• L1 data cache: 16KB, 8-way set associative, 64 byte blocks
  1 cycle access time for cache hit
• 4 cycles latency for L1 cache hit memory access
• L2 unified cache: 1MB, 8-way set associative, 64 byte blocks
  ~10 cycles access time for L2 cache hit
• Main memory: 2GB
  ~50-100 cycles access time
• 146 GB hard disk

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Frank Pfenning