Range Sensor Chip
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Contact:
brajovic@cs.cmu.edu
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The chip layout follows the general architecture of the sensor. WTA rows with arrays of photodetectors can be seen on the left. The peak detectors and digital dual-ported memory are on the right. Here we show the drawing of the layout together with an actual micrograph of 6 pixels. Top area in each pixel is the photodetector, while the bottom is processing circuitry. The pixel fill factor is about 50%. |
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