Copyright: 16c7x Help ® 1994 TRISYS, Inc.


Contents
PIC 16c8x Help,  ver 1.1 by TRISYS, Inc.

PIC 16c8x Instruction Set

Special Purpose Registers

Glossary

Index

Other Products By Trisys

Trademarks and Tradenames

This help file is not intended to replace the Microchip Inc data sheets, but to provide quick on-line overview for the instruction set and special purpose register bit definitions.

The set of processor help files provided by TRISYS are part of the MicroView development environment and the Assemble! IDE assembler. These help files can be downloaded to update the development environments to the latest help files available.


Instructions
Instructions      (PIC 16c8x)

The following instructions are available for the PIC 16c8x processor famly.

ADDLW  k

ADDWF  f,d

ANDLW  k

ANDWF  f,d

BCF  f,b

BSF  f,b

BTFSC  f,b

BTFSS  f,b

CALL  k

CLRF  f

CLRW

CLRWDT

COMF  f,d

DECF  f,d

DECFSZ  f,d

GOTO  k

INCF  f,d

INCFSZ  f,d

IORLW  k

IORWF  f

MOVF  f,d

MOVLW  k

MOVWF  f

NOP

OPTION

RETFIE

RETLW  k

RETURN

RLF  f,d

RRF  f,d

SLEEP

SUBLW  k

SUBWF  f

SWAPF  f,d

TRIS  f

XORLW  k

XORWF  f


ADDLW  k
ADDLW  k      (PIC 16c8x)

The contents of the W register are added to the eight bit literal "k" and the result is placed in the W register.

Syntax:

ADDLW  k
where,
k,	is a 8 bit literal.

Operation:

(W + k) -> W

Status Affected

•	C - Set when addition results in value greater than 0xff. (255).

•	DC - Set when lower nibble of W and literal added together are greater than nine, cleared otherwise.

•	Z - Set when result is zero, cleared otherwise.

Field Definition:

11  111x  kkkk kkkk

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See also:

ADDWF


ADDWF
ADDWF  f,d      (PIC 16c8x)

Add the contents of the W register to register “f”. If “d” is 0 the result is stored in the W register. If “d” is 1 the result is stored back in register “f”.

Syntax:

ADDWF	f,d
where,
f,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

W + f  -> d

Status Affected:

•	Z - Set when result is zero, cleared otherwise.

•	DC - Set when lower nibble of W and F added together are greater than nine, cleared otherwise.

•	C - Set when addition results in value greater than 0xff. (255).

Field Definition:

00 0111 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See also:

ADDLW

SUBWF


SUBWF
SUBWF  f,d      (PIC 16c8x)

Subtract ( 2's complement method) the W register from register “f”.  If “d” is 0 the result is stored in the W register.  If “d” is 1 the result is stored back in register 	f”.

Syntax:

SUBWF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f - W) -> d

Status:

•	Z - Set if result is zero.

•	DC - Set if lower nibble of 'f' minus lower nibble of W is positive.

•	C - Set if result is positive.

Field Definition:

00 0010 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

ADDWF


ANDLW
ANDLW  k      (PIC 16c8x)

The contents of W register are AND'ed with the eight bit literal “k”.  The results is placed in the W register.

Syntax:

ANDLW	k
where,
k is a literal (0-255)

Operation:

(W .AND. k) -> W

Status:

•	Z - Set if result is zero, cleared otherwise.

Field Definition:

11 1001 kkkk kkkk

Cycles:

1

See Also:

ANDWF


ANDWF
ANDWF  f,d      (PIC 16c8x)

AND the W register with “f”.  If “d” is 0 the result is stored in the W register. If “d” is 1 the result is stored back in register “f”.

Syntax:

ANDWF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(W .AND. f)  -> d

Status:

•	Z - Set if result is zero, cleared otherwise.

Field Definition:

00  0101  dfff  ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

ANDLW


BCF
BCF  f,b      (PIC 16c8x)

Bit “b” in register “f” is reset to 0.

Syntax:

BCF	f,b
where,
f ,	is a file register,
b,	bit number to reset (7..0).

Operation:

0  -> f(b)

Status:

None

Field Definition:

01 00bb bfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

BSF

BTFSC

BTFSS


BSF
BSF  f,b      (PIC 16c8x)

Bit “b” in register “f” is set to 1.

Syntax:

BSF	f,b
where,
f ,	is a file register,
b,	bit number to set (7..0).

Operation:

1  -> f(b)

Status:

None.

Field Definition:

01 01bb bfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

BCF

BTFSC

BTFSS


BTFSC
BTFSC  f,b      (PIC 16c8x)

If bit “b” in register “f” is “0” then the next instruction is skipped.

Syntax:

BTFSC	f,b
where,
f ,	is a file register,
b,	bit to test (7..0).

Operation:

skip next instruction if  f(b) = 0

Status:

None.

Field Definition:

01 10bb bfff ffff

Cycles:

If bit “b” is “0”, the next instruction prefetched during the current instruction execution is discarded and a NOP is executed making this a 2 cycle instruction. Otherwise it is a one cycle instruction.

Note:

When tested bit is zero, the prefetch is cleared to zero (NOP). This effectively blanks out the next instruction to be executed; thereby, performing the skip.

See Also:

BCF

BSF

BTFSS


BTFSS
BTFSS  f,b      (PIC 16c8x)

If bit “b” in register “f” is “1” then the next instruction is skipped.

Syntax:

BTFSS	f,b
where,
f ,	is a file register,
b,	bit to test (7..0).

Operation:

Skip next instruction if  f(b) = 1

Status:

None.

Field Definition:

01 11bb bfff ffff

Cycles:

If bit “b” is “1”, the next instruction prefetched during the current instruction execution is discarded and a NOP is executed making this a 2 cycle instruction. Otherwise it is a one cycle instruction.

Note:

When tested bit is one, the prefetch is cleared to zero (NOP). This effectively blanks out the next instruction to be executed; thereby, performing the skip.

See Also:

BCF

BSF

BTFSC


CALL
CALL  k      (PIC 16c8x)

Subroutine Call.  First, return address (PC+1) is pushed on the stack.   The eleven bit value is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH (f03).  CALL is a two cycle instruciton.

Syntax:

CALL	k
where,
k          is a 11 bit address.

Operation:

PC+ 1 -> TOS; k -> PC<10:0>, PCLATH <4:3> -> PC<12:11>

Status:

None

Field Definition:

10 0kkk kkkk kkkk

Cycles:

2

See Also:

RETLW

GOTO


RETLW
RETLW  k      (PIC 16c8x)

Return, place Literal in W

Syntax:

RETLW	k
where,
k is a literal (0-255)

Operation:

k -> W; TOS -> PC;

Status:

None

Field Definition:

11 01xx kkkk kkkk

Cycles:

2

Note:

The RETLW instruction loads all the bits of the PC; therefore, a RETLW can return to any page location.

See Also:

CALL


GOTO
GOTO  k      (PIC 16c8x)

GOTO address.

Syntax:

GOTO	k
where,
k is an address, (k is eleven bits, i.e., k<10:0>).

Operation:

k -> PC<10:0>, PCLATH<4:3> -> PC<12:11>

Status:

None

Field Definition:

10 1kkk kkkk kkkk

Cycles:

2

See Also:

CALL


CLRF
CLRF  f      (PIC 16c8x)

Clear register f.

Syntax:

CLRF	f
where,
f ,	is a file register,

Operation:

00h  -> f

Status:

None.

Field Definition:

00 0001 1fff ffff

Cycles:

One cycle instruction if 'f' is not the PC (register 2); otherwise, it is a two cycle instruction.

See Also:

CLRW


CLRW
CLRW      (PIC 16c8x)

Clear W.

Syntax:

CLRW

Operation:

00h  -> w

Status:

•	Z - Always set.

Field Definition:

00 0001 0xxx xxxx

Cycles:

1

See Also:

CLRF


CLRWDT
CLRWDT      (PIC 16c8x)

Clear Watchdog Timer

Syntax:

CLRWDT

Operation:

1 -> TO, 1 -> PD;

Status:

•	TO - Always set.

•	PD - Always set.

Field Definition:

00 0000 0110 0100

Cycles:

1

See Also:

SLEEP


SLEEP
SLEEP      (PIC 16c8x)

The power down status bit (PD) is cleared.  Time-out status bit (TO) is Set.  Watchdog Timer and its prescaler are cleared.

Syntax:

SLEEP

Operation:

0 -> PD; 1 -> TO;

Status:

•	TO - Always set.

•	PD - Always cleared.

Field Definition:

00 0000 0110 0011

Cycles:

1

See Also:


COMF
COMF  f,d      (PIC 16c8x)

The contents of register “f” are complemented.  If “d” is a 0 the result is stored in W.  If “d” is 1 the result is stored back in register “f”.

Syntax:

COMF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(not f)  -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 1001 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See also:


DECF
DECF  f,d      (PIC 16c8x)

Decrement register “f”.  If “d” is a 0 the result is stored in W.  If “d” is 1 the result is stored back in register “f”.

Syntax:

DECF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f - 1)  -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 0011 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

DECFSZ

INCF


DECFSZ
DECFSZ  f,d      (PIC 16c8x)

The contents of register “f” are decremented.  If “ d” is 0 the result is placed in the W register.  If “d” is 1 the result is placed back in register “f”.  If the result is 0 the next instruction is skipped.

Syntax:

DECFSZ	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f - 1)  -> d; skip if result = 0

Status:

None.

Field Definition:

00 1011 dfff ffff

Cycles:

If the result is 0, the next instruction, which is already fetched is discarded.  A NOP is executed instead making it a two cycle instruction. If the result is not 0 then it is a one cycle instruction.

See Also:

DECF


INCF
INCF  f,d      (PIC 16c8x)

The contents of register “f” are incremented.  If “ d” is 0 the result is placed in the W register.  If “d” is 1 the result is placed back in register “f”.

Syntax:

INCF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f + 1)  -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 1010 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

INCFSZ

DECF


INCFSZ
INCFSZ  f,d      (PIC 16c8x)

The contents of register “f” are incremented. If “ d” is 0, the result is placed in the W register.  If “d” is 1 the result is placed back in register “f”.  If the result is 0 the next instruction is skipped.

Syntax:

INCFSZ	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f + 1)  -> d, skip if result = 0

Status:

None.

Field Definition:

00 1111 dfff ffff

Cycles:

If the result is 0, the next instruction, which is already fetched is discarded.  A NOP is executed instead making it a two cycle instruction. Otherwise it is a one cycle instruction.

See Also:

INCF

DECFSZ


IORLW
IORLW  k      (PIC 16c8x)

The contents of the W register are OR'ed with the eight bit literal “k”.  The result is placed in the W register.

Syntax:

IORLW	k
where,
k is literal.

Operation:

(W .OR. k) -> W

Status:

•	Z - Set if result is zero.

Field Definition:

11 1000 kkkk kkkk

Cycles:

1

See Also:

XORLW

XORWF

ANDWF

ANDLW


XORLW
XORLW  k      (PIC 16c8x)

The contents of the W register are XOR'ed with the eight bit literal “k”.  The result is placed in the W register.

Syntax:

XORLW	k
where,
k is a literal (0-255).

Operation:

(W .XOR. k) -> W;

Status:

•	Z - Set if result is zero.

Field Definition:

11 1010 kkkk kkkk

Cycles:

1

See Also:

IORLW

XORWF

ANDWF

ANDLW


XORWF
XORWF  f,d      (PIC 16c8x)

Exclusive OR the contents of the W register with register “f”.  If “d” is 0 the result is stored in the W register.  If “d” is 1 the result is stored back in register “f”.

Syntax:

XORWF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(W .XOR. f) -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 0110 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

IORLW

XORLW

ANDWF

ANDLW


IORWF
IORWF  f,d      (PIC 16c8x)

Inclusive OR the W register with register “f”.  If “d” is 0 the result is stored in the W register.  If “d” is 1 the result is stored back in register “f”.

Syntax:

IORWF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(W .OR. f)  -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 0100 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:


MOVF
MOVF  f,d      (PIC 16c8x)

The contents of register “f” are moved.  If “d” is 0 the result is stored in the W register.  If “d” is 1 the result is stored back in register “f”.

Syntax:

MOVF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

(f)  -> d

Status:

•	Z - Set if result is zero.

Field Definition:

00 1000 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

Note:

The MOVF instruction with the destination set to be the file register is useful to test if the register is zero.

See Also:

MOVWF

MOVLW


MOVWF
MOVWF  f      (PIC 16c8x)

Move data from W register to register “f”.

Syntax:

MOVWF	f
where,
f ,	is a file register.

Operation:

W  -> d

Status:

None

Field Definition:

00 0000 1fff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

MOVLW

MOVF


MOVLW
MOVLW  k   (16c8x)

The eight bit literal is placed in W.

Syntax:

MOVLW	k
where,
k is literal.

Operation:

k -> W

Status:

None

Field Definition:

11 00xx kkkk kkkk

Cycles:

1

See Also:

MOVF

MOVWF


NOP
NOP      (PIC 16c8x)

No Operation

Syntax:

NOP

Operation:

No Operation

Status:

None

Field Definition:

00 0000 0xx0 0000

Cycles:

1

See Also:


OPTION
OPTION      (PIC 16c8x)

Load OPTION register with W.

To maintain upward compatibility with future 16cxx products, to not use this instruction.

Syntax:

OPTION

Operation:

W -> OPTION register

Status:

None

Field Definition:

00 0000 0110 0010

Cycles:

1

See Also:


RETFIE
RETFIE      (PIC 16c8x)

Return from interrupt. Stack is popped and the top of the stack (TOS) is loaded into the PC. Interrups are enabled by setting the GIE bit.

Syntax

RETFIE

Operation:

TOS -> PC, 1 -> GIE

Status:

•	GLINTD

Field Defintion:

00 0000 0000 1001

Cycles:

2

See Also:

RETURN


RETURN
RETURN      (PIC 16c8x)

Return from subroutine. Thee stack is popped an the top of the stack (TOS) is loaded iinto the program counter.

Syntax:

RETURN

Operation:

TOS -> PC

Status:

none

Field Defintions:

00 0000 0000 1000

Cycles

2

See Also

RETFIE


RLF
RLF  f,d      (PIC 16c8x)

The contents of register “f” are rotated one bit to the left through the Carry Flag.  If “d” is 0 the result is placed in the W register.  If “d” is 1 the result is stored back in register “f”.

Syntax:

RLF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

f<n> -> d<n+1>, f<7> -> C, C -> d<0>;

Status:

•	C - Set if one rotated into carry.

Field Definition:

00 1101 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

RRF

SWAPF


RRF
RRF  f,d      (PIC 16c8x)

The contents of register “f” are rotated one bit to the right through the Carry Flag.  If “d” is 0 the result is placed in the W register.  If “d” is 1 the result is stored back in register “f”.

Syntax:

RRF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

f<n> -> d<n-1>, f<0> -> C, C -> d<7>;

Status:

•	C - Set if one rotated into carry.

Field Definition:

00 1100 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

RLF

SWAPF


SWAPF
SWAPF  f,d      (PIC 16c8x)

The upper and lower nibbles of register “f” are exchanged.  If “d” is 0 the result is placed in W register.  If “d” is 1 the result is placed in register “f”.

Syntax:

SWAPF	f,d
where,
f ,	is a file register,
d,	the direction flag ( i.e., 0 = w, 1 = file register ).

Operation:

f<0:3> -> d<4:7>, f<4:7> -> d<0:3>;

Status:

None

Field Definition:

00 1110 dfff ffff

Cycles:

One cycle instruction for non PC destination. If PC is destination then it is a 2 cycle instruction.

See Also:

RLF

RRF


SUBLW
SUBLW      (PIC 16c8x)

The W register is subtracted (2's complement method) from the eight bit literal "k".

Syntax:

SUBLW  k
Where,
k,        is a 8 bit literal.

Operation:

(k - W) -> W

Status Affected:

•	C - Set when addition results in value greater than 0xff. (255).

•	DC - Set when lower nibble of W and literal added together are greater than nine, cleared otherwise.

•	Z - Set when result is zero, cleared otherwise.

Field Definition:

11 110x kkkk kkkk

Cycles:

                  2

See Also

SUBWF


TRIS
TRIS  f      (PIC 16c8x)

Move W into TRIS register.

To maintain upward compatibility with future 16cxx products, do not use this instruction.

Syntax:

TRIS	f
where,
f is  file register 5, 6, or 7 only.

Operation:

W -> TRIS regsiter f;

Status:

None

Field Definition:

00 0000 0110 0fff

Cycles:

1

Note:

A one for a TRIS bit sets the port bit for input. A zero sets port bit for output.

See Also:


Special Purpose Registers
Special Purpose Registers      (PIC 16c8x)

Indirect Address Register (F00 or F80)

RTCC Real-Time Clock Counter (F01)

PCL Register (F02 or F82)

STATUS Register (F03 or F83)

FSR Register (F04 or F84)

PORTA Register (F05)

PORTB Register (F06)

EEDATA Regsiter (F08)

EEADR Register (F09)

PCLATH Register (F0A or F8A)

INTCON Register (F0B or F8B)

OPTION Register (F81)

TRISA Register (F85)

TRISB Register (F86)

EECON1 Register (F88)

EECON2 Register (F89)


Indirect Address Register
Indirect Address Register (F0 & F80)

Any instruction addressing register F0 or F80 will access data pointed to the by file select register (FSR).

•	Reading from F0 (FSR contains 0 when reading from register F0 or F80) returns zero.

•	Writing to F0 (FSR contains 0 when reading from register F0 or F80) results in a NOP but the STATUS register is affected)

A 9 bit indirect address is obtained by concatenating FSR bits <7:0> with the  STATUS register IRP bit <7>.


RTCC Register
Real Time Clock/Counter  RTCC (F01)

Timer Mode

The timer mode selected by setting the RTS bit of the OPTION register to '0'. The RTCC register will increment according to the prescaler value. If the prescaler is not used, the RTCC will increment every instruction cycle (4 quadratures).

Counter Mode

Counter mode is selected by setting the RTS bit of the OPTION register to '1'. When in this mode the RTCC will increment with every rising or falling edge of pin RA4/RTCC.

•	OPTION register RTE = 0 results in increment on rising edge.

•	OPTION register RTE = 1 results in increment on falling edge.

Note: Rising and falling edges are checked across quadratures 2 and 4 only.

RTCC Interrupt

An RTCC interrupt is generated when the RTCC overflows from 0xFF to 0x00. This state sets the INTCON<2> RTIF bit.  This interrupt can be nasked by setting INTCON<5> RTIE to '0'. The RTCC interrupt cannot wake the processor up from SLEEP.

The RTIF bit must be cleared before re-enabling the interrupt.

See also:

Prescaler


PCL Register
PCL Register (F2 & F82)

The PC is a 13 bit wide counter. The PCL is the low byte of the PC and is readable and writeable via the PCL register (F02 or F08). The high byte of the PC is addressable via the PCLATH (F0A) register. The PC is loaded differently under the two conditions detailed below.

1 	If PCL is modified as the result of an instruction being placed in the PCL register, PC <7:0> are loaded as a result of the instruction and PC<12:8> are loaded from  PCLATH<4:0>.

2 	If PCL is modified as a result of the GOTO or CALL instructions, PC<10:0> are loaded from the opcode of the instruction and PC<12:11> are loaded from PCLATH<4:3>.


STATUS Register
STATUS Register (F03 & F83)

The status register contains the arithmetic status of the ALU, RESET status, and page select bits. The status is updated after every instruction (Q4). Writing to the status register may produce unexpected results, for example; when an instruction which effects the zero bit writes a zero to the status register, the value stored int he STATUS register will have the zero bit set. The STATUS register will not be set to zero as may be expected.

Register Bit Fields

<7>     <6>     <5>     <4>     <3>     <2>     <1>     <0>
IRP     RP1     RP0     TO      PD       Z      DC       C

•	IRP: Register page select bits for indriect addressing:
0 - Page 0,1 (00h - FFh)
1 - Page 2,3 (100h - 1FFh)

•	RP1 & RP0: Register page select bits.
00 : Page 0 (00h  - 7Fh)
01 : Page 1 (80h  - FFh)
10 : Page 2 (100h - 17Fh)
11 : Page 3 (180h - 1FFh)

•	TO : Time-Out bit. Set to '1' during power up and by the CLRWDT and SLEEP instructions. Reset to '0' upon watchdog timer time out. This bit is not writeable.

•	PD: Power Down bit. Set to '1' during power up or by CLRWDT. Reset to '0' by the SLEEP instruction.

•	Z: Zero bit. Set if the result of an arithmetic or logic operation is zero, cleared otherwise. Many instructions may result in a zero result but do not set the Z bit; be sure to check the instruction to see if it effects this bit, some do not.

•	DC: Digit Carry/Borrow Bit. For instructions which effect the DC bit, DC is set if there is a cary out from bit 4 of the resultant. (Useful for BCD calculations)

•	Carry/Borrrow Bit. Set if there is a carry out from the most significant bit of the resultant.


FSR  Register
FSR  Register (F04 & F84)

This register is used with the Indirect Register (F00) reads and writes to perform an indriect read or write to the file registers. The destination of an instruction with F00 specified uses the Indirect Register Page bit (IRP of the STATUS<7>) and the FSR to determine which register to access. This instruction is available from either Register Bank 1 or Register Bank 2.


PORTA  Register
PORTA  Register (F05)

PORTA is a 5 bit wide port with pins RA0 - RA4. Port pins RA<3:0> are bidirectional whereas RA4 has an open-collector output. TRISA controls the direction of the PORTA bits.


PORTB Register
PORTB Register (F06)

PORTB is an 8-bit wide bidirectional port. TRISB sets the individual PORTB pins to either input or output.

PORTB has an interrupt on change feature on pins PORTB<7:4>. At Q1 the pins are sampled and compared with the old latched values. If they are different, an RBIF interrupt is generated. Any pin configured as output, see TRISB, is excluded from comparison. The interrupt can be cleared by either of the following methods:

1 	Disable the interrupt by clearing RBIE.

2 	Clear RBIF bit.

or

1 	Read PORTB ending mismatch condition.

2 	Clear RBIF bit.


EEDATA Regsiter

This register holds the data to be written to EEPROM. This register in addition to EEADR and EECON1 and EECON2 are used to write and read from EEPROM


EEADR Register

This register holds the address of the data to be written to EEPROM. This register in addition to EEDATA and EECON1 and EECON2 are used to write and read from EEPROM


PCLATH  Register

The PCLATH register holds the upper bits of the PC. See the PCL register for more info.


INTCON  Register
INTCON : Interrupt Control Register

The bits of the INTCON are sumarized below:

<7>     <6>     <5>     <4>     <3>     <2>     <1>     <0>
GIE     EEIE    RTIE    INTE    RBIE    RTIF    INTF    RBIF


OPTION  Register
OPTION  Register (F81)

The OPTION register is a readable and writable register which contains control bits to configure the prescaler, external INT interrupt, RTCC, and the weak pull-ups of PORTB. The bits are defined as follows.

<7>    <6>    <5>    <4>    <3>    <2>    <1>    <0>
PBPU  INTEDG  RTS    RTE    PSA    PS2    PS1    PS0

•	PBPU : PORTB pull-up enable. If '0', pull-ups are enabled by individual port-latch values. If '1', pull-ups are disabled overriding port latch values.

•	INTEDG : INT interrupt edge select. If '0' interrupt on falling edge. If '1' interrupt on rising edge.

•	RTS : RTCC signal source. If '0', source is internal instruction cycle clock (CLKOUT). If '1', source is on transition on RA4/RTCC pin.

•	RTE : RTCC signal edge. If '0', increment RTCC on low to high transition of RA4/RTCC pin. If '1', increment RTCC on high to low transition of RA4/RTCC pin.

•	PSA : Prescaler assignment bit. If '0', prescaler assigned to RTCC. If '1', prescaler assigned to WDT.

•	PS2, PS1, PS0 : Prescaler assignemnt value. See table below.

Prescaler Value | RTCC Rate | WDT Rate
   0,0,0        |   1:2     |  1:1
   0,0,1        |   1:4     |  1:2
   0,1,0        |   1:8     |  1:4
   0,1,1        |   1:16    |  1:8
   1,0,0        |   1:32    |  1:16
   1,0,1        |   1:64    |  1:32
   1,1,0        |   1:128   |  1:64
   1,1,1        |   1:256   |  1:128

See also:

OPTION instruction


TRISA  Register

The TRISA register controls the pins of PORTA to be input or output. A '0' in TRISA sets the corresponding PORTA pin to output. A '1' in TRISA sets the corresponding PORTA pin to input.


TRISB  Register

The TRISB register controls the pins of PORTB to be input or output. A '0' in TRISB sets the corresponding PORTB pin to output. A '1' in TRISB sets the corresponding PORTB pin to input.


EECON1 Register

The bit representation of the EECON1 register is as follows.

 <7>     <6>     <5>     <4>     <3>     <2>     <1>     <0>
  U       U       U      EEIF   WRERR    WREN    WR      RD


EECON2 Register

EECON2 is not a physical register. Reading EECON2 will read '0's.


Glossary

A

ADC

ADCON1

ADCS0

ADCS1

ADIE

ADIF

ADON

ADRES

C

C

CALL

CHS0

CHS1

CLRWDT

D

DC

E

EEADR

EECON1

EECON2

EEDATA

EEIE

EEIF

F

FSR

G

GIE

GO/DONE

GOTO

I

Indirect Register

INTCON

INTE

INTEDG

INTF

IRP

P

PBPU

PC.

PCFG0

PCFG1

PCL

PCLATH

PD

PS0

PS1

PS2

PSA

R

RBIE

RBIF

RD

Res

RP0

RP1

RTE

RTIE

RTIF

RTS

S

SLEEP

T

TO

U

U

W

WDT

WR

WREN

WRERR

Z

Z


Index

A

ADDLW  k

ADDWF

ANDLW

ANDWF

B

BCF

BSF

BTFSC

BTFSS

C

CALL

CLRF

CLRW

CLRWDT

COMF

Contents

D

DECF

DECFSZ

E

EEADR Register

EECON1 Register

EECON2 Register

EEDATA Regsiter

F

FSR  Register

G

Glossary

GOTO

H

Hints and Tips

How to contact us

How to Contribute

I

INCF

INCFSZ

Index

Indirect Address Register

Instructions

INTCON  Register

IORLW

IORWF

M

MOVF

MOVLW

MOVWF

N

NOP

O

OPTION  Register

OPTION

Other Products By Trisys

P

PCL Register

PCLATH  Register

PORTA  Register

PORTB Register

R

RETFIE

RETLW

RETURN

RLF

RRF

RTCC Register

S

SLEEP

Special Purpose Registers

STATUS Register

SUBLW

SUBWF

SWAPF

T

Trademarks and Tradenames

TRIS

TRISA  Register

TRISB  Register

U

Useful Code Bits And Pieces

X

XORLW

XORWF


Other Products By Trisys

MicroView Development Environment

The MicroView development environment is a full featured editor, macro-assembler, and simulator wrapped up in a Windows 3.1 MDI environment. The simulation supports all the 5x series of processors. Support for other processors will be added in future releases.

Macro Assembler

The macro assembler is Windows 3.1 MDI compliant integrated editor and macro-assembler for those PIC-Mate or PIC-Master owners who do not need the simulation support but would like an integrated editor and assembler.

Shareware versions of these programs can be found on the Microchip BBS, 3rdparty file library.

How to contact us and how to order.


How to contact us

Trisys can be contacted through the Microchip Technologies Inc. bulletin board. Address Email to Trisys or post questions within the "3rdparty" special forum. Responses will be posted usually within one working day. Instructions for logging into the bulletin board can be found in the Microchip data books.

Trisys may be FAXed at 1-602-581-1760.

Internet Email to: trisys@ramp.com

To order by phone (CREDIT CARD ORDERS ONLY)

Order by phone with MasterCharge, Visa, American Express, or Discover from Public (software) Library by calling 1-800-2424-PsL or 1-713-524-6394 or by FAX to 1-713-524-6398 or by CIS Email to 71355,470. You can also mail credit card orders to PsL at P.O. Box 35705, Houston, TX 77235-5705.

Ask for MicroView™, Product # 11332.
or
Ask for Assemble!, Product #11358

The above numbers are for credit card orders only!

Any questions about the status of the shipment of the order, refunds, registration options, product details, technical support, volume discounts, dealer pricing, site licenses, etc, should be directed to 1-602-581-1760. Or by FAX to 1-602-581-1760 (same number for voice and FAX). Or by CIS Email to 74547,2447

To insure that you get the latest version, PsL will notify us the day of your order and we will ship the product directly to you.


Trademarks and Tradenames

The Trisys logo, MicroView and the name Trisys are trademarks and tradenames of Trisys.

Microchip and PIC are the trademark and tradename of Microchip Technologies Inc.

Parallax is the trademark and tradename of Parallax, Inc.

Windows 3.1 is the trademark of Microsoft.


Hints and Tips

None yet... waiting for some responses. If you have any, respond to the Microchip BBS in the third party forum. Reference the PIC help.


How to Contribute

This help file is intended to be a running compilation of ideas and helpful hints. To make it work, the users of the PIC 16c8x processor will have to contribute. It's easy to see what the topics are (look at the help file). If you have a few seconds. Put in your two cents worth.

Send Email to David Foringer on the Microchip BBS or put your comments in the third party forum. I'm up there often and will try to incorporate the good information (I'm the judge) in updates to this help file.

Lets make this a useful help file for all to use!!


Useful Code Bits And Pieces
Useful Code Bits & Pieces

None yet.. Waiting for some ideas..


ADC

Analog Digital Converter


ADCON1

<ADCON1  Register>


ADCS0

ADCS1 & ADCS0 : A/D conversion clock select. ADCON0<7:6>


ADCS1

ADCS1 & ADCS0 : A/D conversion clock select. ADCON0 <7:6>


ADIE

ADIE : A/D conversion interrupt enable bit. '0' disables A/D interrupt. '1' enables A/D interrupt. (INTCON<6>)


ADIF

ADIF : A/D conversion complete interrupt flag. Set when conversion is complete. Must be reset in software. ADCON0<1>


ADON

ADON : A/D On. ADON = 0 A/D converter is off. ADON = 1 A/D converter is on. ADCON0<0>


ADRES

A/D Result Register


C

Carry/Borrrow Bit. Set if there is a carry out from the most significant bit of the resultant.


CALL

<CALL>


CHS0

CHS1 & CHS0 : Analog channel select. ADCON0 <4:3>


CHS1

CHS1 & CHS0 : Analog channel select. ADCON0 <4:3>


CLRWDT

<CLRWDT>


DC

DC: Digit Carry/Borrow Bit. For instructions which effect the DC bit, DC is set if there is a cary out from bit 4 of the resultant. (Useful for BCD calculations)


EEADR

<EEADR Register>


EECON1

<EECON1 Register>


EECON2

<EECON2 Register>


EEDATA

<EEDATA Regsiter>


EEIE

INTCON<6>.  EEPROM write interrupt enable bit. A '0' disables EEIF interrupt. A '1' enables EEIF interrupt.


EEIF

EECON1<4>.  EEPROM write completion interrupt flag bit. Set when write is completed. Must be reset in software. Corresponding enable bit is EEIE in INTCON<> register


FSR

<FSR  Register>


GIE

INTCON<7>.   Global interrupt enable. '0' disables interrupts. '1' enables interrupts.


GO/DONE

GO/-DONE : Set to begin A/D conversion. Cleared by hardware when conversion complete and ADIF will be set. ADCON0 <2>


GOTO

<GOTO>


Indirect Register

<Indirect Address Register>


INTCON

<INTCON  Register>


INTE

INTCON<4>   INT interrupt enable bit. '0' disables interrupt. '1' enables interrupt.


INTEDG

INTEDG : INT interrupt edge select. If '0' interrupt on falling edge. If '1' interrupt on rising edge.


INTF

INTCON<1>  INT interrupt flag. Set when INT interrupt occurs. Must be reset in software.


IRP

IRP: Register page select bits for indriect addressing:0 - Page 0,1 (00h - FFh)1 - Page 2,3 (100h - 1FFh)


PBPU

PBPU : PORTB pull-up enable. If '0' pull-ups are enabled by individual port-latch values. If '1' pull-ups are disabled overriding port latch values.


PC.

Program Counter (13 bits for 16c71)


PCFG0

<ADCON0  Register>


PCFG1

<ADCON1  Register>


PCL

<PCL Register>


PCLATH

<PCLATH  Register>


PD

PD: Power Down bit. Set to '1' during power up or by CLRWDT. Reset to '0' by the SLEEP instruction.


PS0

<OPTION  Register>


PS1

<OPTION  Register>


PS2

<OPTION  Register>


PSA

PSA : Prescaler assignment bit. If '0', prescaler assigned to RTCC. If '1', prescaler assigned to WDT.


RBIE

(INTCON<3>  RBIF interrupt enable bit. '0' disables PORTB interrupt on change. '1' enables PORTB interrupt on change.


RBIF

INTCON<0>   RB port change interrupt flag. This flag must be reset in software to clear interrupt.


RD

EECON<0>  Read control bit.  If '1', initiates an EEPROM read. Read takes on clock cycle. RD is cleared in hardware. RD bit can only be set, not cleared, in software.


Res

Res - Reserved


RP0

RP1 & RP0: Register page select bits.	00 : Page 0 (00h  - 7Fh)	01 : Page 1 (80h  - FFh)	10 : Page 2 (100h - 17Fh)	11 : Page 3 (180h - 1FFh)


RP1

RP1 & RP0: Register page select bits.	00 : Page 0 (00h  - 7Fh)	01 : Page 1 (80h  - FFh)	10 : Page 2 (100h - 17Fh)	11 : Page 3 (180h - 1FFh)


RTE

RTE : RTCC signal edge. If '0', increment RTCC on low to high transition of RA4/RTCC pin. If '1', increment RTCC on high to low transition of RA4/RTCC pin.


RTIE

INTCON<5>  RTCC interrupt enable bit. '0' disables RTCC interrupt. '1' enables RTCC interrupt.


RTIF

INTCON<2>   RTCC overflow interrupt flag. Set when RTCC overflows. Must be reset in software


RTS

RTS : RTCC signal source. If '0' source is internal instruction cycle clock (CLKOUT). If '1' source is on transition on RA4/RTCC pin.


SLEEP

<SLEEP>


TO

TO : Time-Out bit. Set to '1' during power up and by the CLRWDT and SLEEP instructions. Reset to '0' upon watchdog timer time out. This bit is not writeable.


U

Unused.


WDT

WDT : Watch Dog Timer.


WR

EECON1<1>  Write control bit.  If '1' will initiate a write cycle.  The bit is cleared by hardware once write is complete.  WR bit can only be set, not cleared, in software.


WREN

EECON1<2>  EEPROM write enable bit.  If '0', inhibits write to the data EEPROM.  If '1', allows write operation.


WRERR

EECON1<3>  WRERR error flag is set if a write operation is prematurely terminated by a -MCLR reset or by a WDT reset during normal operation.


Z

Z: Zero bit. Set if the result of an arithmetic or logic operation is zero, cleared otherwise. Many instructions may result in a zero result but do not set the Z bit; be sure to check the instruction to see if it effects this bit, some do not.