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15-740 Spring '18
In-Class Discussions
Advice
Here is some advice on how to lead a discussion.
Slides from the in-class presentations:
Once you have chosen a topic that looks interesting,
Look over the papers in recent conferences to find the most relevant papers to read.
View these papers as a suggestion or starting point. You are free and encouraged to select the papers that will be most relevant to your project,
and to select entirely new topics not listed below.
ISCA 2017.
MICRO 2017.
ASPLOS 2017.
HPCA 2017.
List of papers
- Hari Cherupalli (University of Minnesota), Henry Duwe, Weidong Ye, Rakesh Kumar (University of Illinois), John Sartori (University of Minnesota)
Bespoke Processors for Applications with Ultra-low Area and Power Constraints
ISCA 2017
- Tae Jun Ham (Princeton University), Lisa Wu (University of California, Berkeley), Narayanan Sundaram (Intel), Nadathur Satish (Intel), Margaret Martonosi (Princeton University)
Graphicianado: A High-Performance and Energy-Efficient Accelerator for Graph Analytics, in
MICRO 2016 (best paper)
- Tony Nowatzki (UCLA), Vinay Gangadhar (Wisconsin-Madison), Karthikeyan Sankaralingam (Wisconsin-Madison), Greg Wright (Qualcomm)
Domain Specialization is Generally Unnecessary for Accelerators
IEEE MICRO 2017
- Advait Madhavan, Timothy Sherwood, Dmitri Strukov
Race logic: a hardware acceleration for dynamic programming algorithms,
ISCA 2014
Neural Accelerators
- Norman P. Jouppi et al (Google)
In-Datacenter Performance Analysis of a Tensor Processing Unit
ISCA 2017
-
Hardik Sharma, Jongse Park, Divya Mahajan, Emmanuel Amaro, Joon Kyung Kim, Chenkai Shao (Georgia Institute of Technology), Asit Mishra (Intel), Hadi Esmaeilzadeh (Georgia Institute of Technology)
From High-Level Deep Neural Models to FPGAs
MICRO 2016
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Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz (Stanford), William J. Dally (Stanford/NVIDIA)
EIE: Efficient Inference Engine on Compressed Deep Neural Network
ISCA 2016
- Thomas J. Repetti, Joao Pedro Cerqueira, Martha A. Kim, Mingoo Seok (Columbia)
Pipelining a Triggered Processing Element in
MICRO 2017
- Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matt Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun (Stanford University)
Plasticine: A Reconfigurable Architecture for Parallel Patterns, in
ISCA 2017
- Tony Nowatzki (UCLA), Vinay Gangadhar, Newsha Ardalani, Karthikeyan Sankaralingam (University of Wisconsin, Madison)
Stream-Dataflow Acceleration,
ISCA 2017
- Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric,
ISCA 2016
- Raghu Prabhakar, David Koeplinger, Yaqi Zhang, Christina Delimitrou, Christos Kozyrakis, Kunle Olukotun
Automatic Generation of Efficient Accelerators for Reconfigurable Hardware,
ISCA 2016
- Adrian M. Caulfield, Eric S. Chung, Andrew Putnam, Hari Angepat, Jeremy Fowers, Michael Haselman, Stephen Heil, Matt Humphrey, Puneet Kaur, Joo-Young Kim, Daniel Lo, Todd Massengill, Kalin Ovtcharov, Michael Papamichael, Lisa Woods, Sitaram Lanka, Derek Chiou, Doug Burger (Microsoft)
A Cloud-Scale Acceleration Architecture,
MICRO 2016
- Sandeep R Agrawal; Sam Idicula; Arun Raghavan; Evangelos Vlachos; Venkatraman Govindaraju; Venkatanathan Varadarajan; Cagri Balkesen; Georgios Giannikis; Charlie Roth:NXP; Nipun Agarwal; Eric Sedlar (Oracle Labs)
A Many-core Architecture for In-Memory Data Processing
MICRO 2017
-
Vivek Seshadri (Microsoft Research India); Donghyuk Lee (NVIDIA Research); Thomas Mullins (Intel); Hasan Hassan (ETH Zurich); Amirali Boroumand (CMU); Jeremie Kim (ETH Zurich); Michael A. Kozuch (Intel); Onur Mutlu (ETH Zurich); Phillip B. Gibbons (CMU); Todd C. Mowry (CMU)
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
MICRO 2017
-
Lifeng Nai, Georgia Institute of Technology;
Ramyad Hadidi, Georgia Institute of Technology;
Jaewoong Sim, Intel Labs;
Hyojong Kim, Georgia Institute of Technology;
Pranith Kumar, Georgia Institute of Technology;
Hyesoon Kim, Georgia Institute of Technology
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
HPCA 2017
Microarchitecture
-
Shruti Padmanabha:University of Michigan; Andrew Lukefahr:University of Michigan; Reetuparna Das:University of Michigan; Scott Mahlke:University of Michigan
MICRO 2017
-
Rakesh Kumar, University of Edinburgh;
Cheng-Chieh Huang, University of Edinburgh;
Boris Grot, University of Edinburgh;
Vijay Nagarajan, University of Edinburgh
Boomerang: A Metadata-Free Architecture for Control Flow Delivery
HPCA 2017
- Arthur Perais (INRIA/IRISA), Fernando A. Endo (INRIA/IRISA), André Seznec (INRIA/IRISA)
Register Sharing for Equality Prediction
MICRO 2016
DRAM and other Memory Technologies
- Mike O'Connor (NVIDIA / UT-Austin), Niladrish Chatterjee, Donghyuk Lee, John Wilson, Aditya Agrawal (NVIDIA), Stephen W. Keckler (NVIDIA / UT-Austin), William J. Dally (NVIDIA / Stanford)
Fine-Grained DRAM: Energy Efficient DRAM for Extreme Bandwidth Systems,
MICRO 2017
- Mario Drumond, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi (EcoCloud, EPFL), Boris Grot (University of Edinburgh), Dionisios Pnevmatikatos (FORTH-ICS & ECE-TUC)
The Mondrian Data Engine,
ISCA 2017
- Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale Patt
Accelerating Dependent Cache Misses with an Enhanced Memory Controller,
ISCA 2016
- Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri Strukov, Yuan Xie, Frederic T. Chong
Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs,
ISCA 2016
- Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, and Mark Horowitz
Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access,
MICRO 2016
Emerging Technologies
-
Ting-Jung Chang:Princeton University; Zhuozhi Yao:Princeton University; Paul J. Jackson:Princeton University; Barry P. Rand:Princeton University; David Wentzlaff:Princeton University
Architectural Tradeoffs for Biodegradable Computing
MICRO 2017
- Tiancong Wang:NC State University; Sakthikumaran Sambasivam:NC State University; Yan Solihin:NC State University; James Tuck:NC State University.
Hardware Supported Persistent Object Address Translation
MICRO 2017
- Seunghee Shin, Satish Kumar Tirukkovalluri, James Tuck, Yan Solihin (North Carolina State University)
Proteus: A Flexible and Fast Software Supported Hardware Logging approach for NVM,
MICRO 2017
- Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, Gabriel H. Loh (*Advanced Micro Devices, Inc.)
There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes, in
ISCA 2017
- Mahdi Nazm Bojnordi and Engin Ipek
Memristive Boltzmann Machine: A Hardware Accelerator for Combinatorial Optimization and Deep Learning,
HPCA 2016
Quantum Computing
- X. Fu et al (Delft)
An Experimental Microarchitecture for a Superconducting Quantum Processor, in
MICRO 2017
-
Swamit S. Tannu:Georgia Tech; Zachary A. Myers:Stanford; Prashant J. Nair:Georgia Tech; Douglas M. Carmean:Microsoft; Moinuddin K. Qureshi:Georgia Tech
Taming the Instruction Bandwidth of Quantum Computers via Hardware-Managed Error Correction
MICRO 2017
-
Ali Javadi-Abhari:Princeton University; Pranav Gokhale:University of Chicago; Adam Holmes:University of Chicago; Diana Franklin:University of Chicago; Kenneth R. Brown:Georgia Institute of Technology; Margaret Martonosi:Princeton University; Frederic T. Chong:University of Chicago
Optimized Surface Code Communication in Superconducting Quantum Computers
MICRO 2017
Architectures and Performance Modeling
- Muhammad Shoaib, Bin Altaf, David A. Wood (AMD Research Advanced Micro Devices, Inc., Computer Sciences Department University of Wisconsin-Madison)
LogCA: A High-Level Performance Model for Hardware Accelerators,
ISCA 2017
-
Rafael K. V. Maeda, Hong Kong University of Science and Technology;
Qiong Cai, Hewlett Packard Labs;
Jiang Xu, Hong Kong University of Science and Technology;
Zhe Wang, Hong Kong University of Science and Technology;
Zhongyuan Tian, Hong Kong University of Science and Technology
Fast and Accurate Exploration of Multi-Level Caches Using Hierarchical Reuse Distance
HPCA 2017
-
Nathan Beckmann and Daniel Sanchez (MIT)
Modeling Cache Performance Beyond LRU
HPCA 2016
-
T. Nowatzki, V. Gangadhar, K. Sankaralingam
Exploring the Potential of Heterogeneous Von Neumann/Dataflow Execution Models.
ISCA 2015
-
Zhen Zheng:Tsinghua University; Chanyoung Oh:University of Seoul; Jidong Zhai:Tsinghua University; Xipeng Shen:North Carolina State University; Youngmin Yi:University of Seoul; Wenguang Chen:Tsinghua University
VersaPipe: A Versatile Programming Framework for Pipelined Computing on GPU
MICRO 2017
- Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel Emer, Daniel Sanchez (Massachusetts Institute of Technology)
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism, in
ISCA 2017
- Jiho Choi, Thomas Shull, Maria J. Garzaran, Josep Torrellas (University of Illinois at Urbana-Champaign)
ShortCut: Architectural Support for Fast Object Access in Scripting Languages, in
ISCA 2017
- Sungpack Hong, Hassan Chafi, Edic Sedlar, and Kunle Olukotun.
Green-Marl: a DSL for easy and efficient graph analysis,
ASPLOS '12
- Ivan Tanasic (Universitat Politecnica de Catalunya / Barcelona Supercomputing Center); Isaac Gelado (NVIDIA); Marc Jorda (Barcelona Supercomputing Center); Eduard Ayguade; Nacho Navarro (Universitat Politecnica de Catalunya / Barcelona Supercomputing Center)
Efficient Exception Handling Support for GPUs,
MICRO 2017
- John Kloosterman, Jon Beaumont, Davoud Anoushe Jamshidi, Jonathan Bailey, Trevor Mudge, Scott Mahlke (Michigan)
RegLess: Just-in-Time Operand Staging for GPUs,
MICRO 2017
- Akhil Arunkumar (ASU), Evgeny Bolotin (NVIDIA), Benjamin Cho (UT Austin), Ugljesa Milic (Barcelona / Universitat Politecnica de Catalunya), Eiman Ebrahimi (NVIDIA), Oreste Villa (NVIDIA), Aamer Jaleel (NVIDIA), Carole-Jean Wu (ASU), David Nellans (NVIDIA)
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability,
ISCA 2017
-
Ahmed ElTantawy and Tor M. Aamodt
MIMD Synchronization on SIMT Architectures
MICRO 2016
-
Izzat El Hajj, Juan Gómez-Luna, Cheng Li, Li-Wen Chang (University of Illinois at Urbana-Champaign), Dejan Milojicic (Hewlett-Packard), Wen-mei Hwu (University of Illinois at Urbana-Champaign)
KLAP: Kernel Launch Aggregation and Promotion for Optimizing Dynamic Parallelism
MICRO 2016
Exploiting Heterogeneous Architectures
- Md E. Haque (Rutgers); Yuxiong He; Sameh Elnikety (MSR); Thu D. Nguyen (Rutgers); Ricardo Bianchini (MSR); Kathryn S. McKinley (Google)
Exploiting Heterogeneity for Tail Latency and Energy Efficiency,
MICRO 2017
-
Ajeya Naithani, Ghent University;
Stijn Eyerman, Intel;
Lieven Eeckhout, Ghent University
Reliability-Aware Scheduling on Heterogeneous Multicore Processors
HPCA 2017
- Ashish Venkat and Dean M. Tullsen
Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor,
ISCA 2014
- Hoda Naghibijouybari; Khaled Khasawneh; Nael Abu-Ghazaleh (UC Riverside)
Constructing and Characterizing Covert Channels on GPGPUs,
MICRO 2017
- Ofir Weisse, Valeria Bertacco, Todd Austin (University of Michigan) in
Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves,
ISCA 2017
- Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas (University of Illinois at Urbana-Champaign)
Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks, in
ISCA 2017
- Mehmet Kayaalp, Meltem Ozsoy, Nael Abu-Ghazaleh, and Dmitry Ponomarev.
Branch regulation: low-overhead protection from code reuse attacks,
Proceedings of the 39th International Symposium on Computer Architecture (ISCA '12).
Warehouse-Scale Computing
- Dibakar Gope, David J. Schlais, Mikko H. Lipasti (Department of Electrical and Computer Engineering University of Wisconsin - Madison)
Architectural Support for Server-Side PHP Processing,
ISCA 2017
-
Mohammad Alian, UIUC;
Ahmed Abulila, UIUC;
Lokesh Jindal, University of Wisconsin-Madison;
Daehoon Kim, UIUC/DGIST;
Nam Sung Kim, UIUC
NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server Architecture
HPCA 2017
-
Qiuyun Llull, Duke University;
Songchun Fan, Duke University;
Seyed Majid Zahedi, Duke University;
Benjamin C. Lee, Duke University
Cooper: Task Colocation with Cooperative Games
HPCA 2017
- Christina Delimitrou, Christos Kozyrakis
HCloud: Resource-Efficient Provisioning in Shared Cloud Systems, in
ASPLOS'16
- Svilen Kaven (Harvard), Juan Pablo Darago (Universidad de Buenos Aires), Kim Hazelwood (Yahoo Labs), Parthasarathy Ranganathan (Google), Tipp Moseley (Google), Gu-Yeon Wei (Harvard), David Brooks (Harvard)
Profiling a warehouse-scale computer in
ISCA'15
- David Lo, Liqun Cheng, Rama Govindaraju, Luiz André Barroso, Christos Kozyrakis
Towards energy proportionality for large-scale latency-critical workloads,
ISCA 2014
Adaptive Cache Replacement
- Nathan Beckmann, Daniel Sanchez
Maximizing Cache Performance Under Uncertainty,
Proceedings of the 23rd IEEE Symposium on High Performance Computer Architecture (HPCA '17).
- Elvira Teran, Zhe Wang, Daniel A. Jiḿenez
Perceptron Learning for Reuse Prediction,
MICRO 2016
- Akanksha Jain, Calvin L
Back to the Future: leveraging Belady's algorithm for improved cache replacement,
Proceedings of the 43rd International Symposium on Computer Architecture (ISCA '16).
- Aamer Jaleel, Kevin B. Theobald, Simon C. Steely, Jr., and Joel Emer.
High performance cache replacement using re-reference interval prediction (RRIP),
Proceedings of the 37th annual international symposium on Computer architecture (ISCA '10).
- Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel Emer
Adaptive Insertion Policies for High Performance Caching,
ISCA '07
Caches and Memory Hierarchies
- Moinuddin Qureshi, Gabriel Loh
Fundamental Latency Trade-offs in Architecting DRAM Caches,
MICRO 2012
- Andreas Sembrant, Erik Hagersten, David Black-Schaffer
The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup,
Proceedings of the 41st International Symposium on Computer Architecture (ISCA '12).
- Nathan Beckmann, Daniel Sanchez
Jigsaw: Scalable Software-defined Caches,
Proceedings of the 22nd international conference on Parallel architectures and compilation techniques (PACT '13).
- Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry.
Base-delta-immediate compression: practical data compression for on-chip caches,
Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12).
- Yatin A. Manerkar (Princeton); Daniel Lustig (NVIDIA); Margaret Martonosi (Princeton); Michael Pellauer (NVIDIA)
RTLCheck: Verifying the Memory Consistency of RTL Designs,
MICRO 2017
- Opeoluwa Matthews; Daniel J. Sorin (Duke University)
Architecting Hierarchical Coherence Protocols for Push-button Parametric Verification,
MICRO 2017
- Matthew D. Sinclair, Johnathan Alsop, Sarita V. Adve (University of Illinois at Urbana-Champaign)
Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems
ISCA 2017
- Hiding the Long Latency of Persist Barriers Using Speculative Execution,
Seunghee Shin, James Tuck, Yan Solihin (Dept. of Electrical and Computer Engineering North Carolina State University)
Hiding the Long Latency of Persist Barriers Using Speculative Execution,
ISCA 2017
- Derek Hower, Blake Hechtman, Bradford Beckmann, Benedict Gaster, Mark Hill, Steven Reinhardt, David Wood
Heterogeneous Race-free Memory Models,
ASPLOS 2014
- Kaisheng Ma, Xueqing Li (Penn State), Jinyang Li, Yongpan Liu, (Tsinghua), Yuan Xie (UCSB), Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan (Penn State)
Incidental Computing on IoT Nonvolatile Processors, in
MICRO 2017
- Matthew Hicks (Virginia Tech)
Clank: Architectural Support for Intermittent Computation, in
ISCA 2017
- Alexei Colin, Brandon Lucia (Carnegie Mellon University), Alanson P. Sample, and Graham Harvey (Disney Research, Pittsburgh)
An Energy-interference-free Hardware-Software Debugger for Intermittent Energy-harvesting Systems, in
ASPLOS '16
- Kaisheng Ma, Xueqing Li (Penn State), Shuangchen Li (UC Santa Barbara), Yongpan Liu (Tsinghua), Jack Sampson (Penn State), Yuan Xie (UC Santa Barbara), Vijaykrishnan Narayanan (Penn State)
Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications
IEEE MICRO 2015
- Yashwant Marathe (UT Austin); Nagendra Gulur (Texas Instruments); Jee Ho Ryoo; Shuang Song; Lizy K. John (UT Austin)
CSALT: Context Switch Aware Large TLB,
MICRO 2017
- Chang Hyun Park, Taekyung Heo, Jungi Jeong, Jaehyuk Huh (School of Computing, KAIST)
Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations, in
ISCA 2017
- Hanna Alam, Tianhao Zhang, Mattan Erez, Yoav Etsion (Technion - Israel Institute of Technology and The University of Texas at Austin)
Do-It-Yourself Virtual Memory Translation, in
ISCA 2017
-
Yuchen Hao, UCLA;
Zhenman Fang, UCLA;
Glenn Reinman, UCLA;
Jason Cong, UCLA
Supporting Address Translation for Accelerator-Centric Architectures
HPCA 2017
- Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrian Cristal, Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky, Michael M. Swift, Osman Ünsal
Redundant Memory Mappings for Fast Access to Large Memories, in
ISCA 2015
I found fewer papers on the following topics from recent conferences. If you are interested in them, please take especially careful effort to find *recent* papers.
- Hwanju Kim, Sangwook Kim, Jinkyu Jeong, Joonwon Lee, Seungryoul Maeng
Demand-based coordinated scheduling for SMP VMs,
ASPLOS '13
- Daniel Sanchez, Richard M. Yoo, and Christos Kozyrakis.
Flexible architectural support for fine-grain scheduling,
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10).
- [Background material:] Sanjeev Kumar, Christopher J. Hughes, and Anthony Nguyen.
Carbon: architectural support for fine-grained parallelism on chip multiprocessors,
Proceedings of the 34th annual international symposium on Computer architecture (ISCA '07).
- Stijn Eyerman and Lieven Eeckhout.
Probabilistic job symbiosis modeling for SMT processor scheduling,
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10).
- F. Ryan Johnson, Radu Stoica, Anastasia Ailamaki, and Todd C. Mowry.
Decoupling contention management from scheduling,
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10).
- Sergey Zhuravlev, Sergey Blagodurov, and Alexandra Fedorova.
Addressing shared resource contention in multicore processors via scheduling,
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10).
Finding and Fixing Software Bugs
- Benjamin Wester, David Devecsery, Peter M. Chen, Jason Flinn, Satish Narayanasamy
Parallelizing data race detection,
ASPLOS '13
- Santosh Nagarakatte, Milo M. K. Martin, and Steve Zdancewic.
Watchdog: hardware for safe and secure manual memory management and full memory safety,
Proceedings of the 39th International Symposium on Computer Architecture (ISCA '12).
- Joseph Devietti, Benjamin P. Wood, Karin Strauss, Luis Ceze, Dan Grossman, and Shaz Qadeer.
RADISH: always-on sound and complete Race Detection in Software and Hardware,
Proceedings of the 39th International Symposium on Computer Architecture (ISCA '12).
- Evangelos Vlachos, Michelle L. Goodstein, Michael A. Kozuch, Shimin Chen, Babak Falsafi, Phillip B. Gibbons, and Todd C. Mowry.
ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications,
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems (ASPLOS '10).
- Wei Zhang, Junghee Lim, Ramya Olichandran, Joel Scherpelz, Guoliang Jin, Shan Lu, and Thomas Reps.
ConSeq: detecting concurrency bugs through sequential errors,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
Optimizing Power and Energy
- Vasileios Kontorinis, Liuyi Eric Zhang, Baris Aksanli, Jack Sampson, Houman Homayoun, Eddie Pettis, Dean M. Tullsen, and Tajana Simunic Rosing.
Managing distributed UPS energy for effective power capping in data centers,
Proceedings of the 39th International Symposium on Computer Architecture (ISCA '12).
- Navin Sharma, Sean Barker, David Irwin, and Prashant Shenoy.
Blink: managing server clusters on intermittent power,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Henry Hoffmann, Stelios Sidiroglou, Michael Carbin, Sasa Misailovic, Anant Agarwal, and Martin Rinard.
Dynamic knobs for responsive power-aware computing,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Song Liu, Karthik Pattabiraman, Thomas Moscibroda, and Benjamin G. Zorn.
Flikker: saving DRAM refresh-power through critical data partitioning,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Qingyuan Deng, David Meisner, Luiz Ramos, Thomas F. Wenisch, and Ricardo Bianchini.
MemScale: active low-power modes for main memory,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Syed Ali Raza Jafri, Gwendolyn Voskuilen, T. N. Vijaykumar
Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies,
ASPLOS '13
- Jared Casper, Tayo Oguntebi, Sungpack Hong, Nathan G. Bronson, Christos Kozyrakis, and Kunle Olukotun.
Hardware acceleration of transactional memory on commodity systems,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Luke Dalessandro, François Carouge, Sean White, Yossi Lev, Mark Moir, Michael L. Scott, and Michael F. Spear.
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory,
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems (ASPLOS '11).
- Amy Wang, Matthew Gaudet, Peng Wu, José Nelson Amaral, Martin Ohmacht, Christopher Barton, Raul Silvera, and Maged Michael.
Evaluation of blue Gene/Q hardware support for transactional memories,
Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12).
- Haris Volos, Andres Jaan Tack, Michael M. Swift, and Shan Lu.
Applying transactional memory to concurrency bugs,
Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '12).
- Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, and Ching-Tsun Chou
DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism,
Proceedings of the 20th international conference on Parallel architectures and compilation techniques (PACT '11).
- Ronald G. Dreslinski, Thomas Manville, Korey Sewell, Reetuparna Das, Nathaniel Pinckney, Sudhir Satpathy, David Blaauw, Dennis Sylvester, and Trevor Mudge.
XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems,
Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12).
- Alberto Ros and Stefanos Kaxiras.
Complexity-effective multicore coherence,
Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12).
- Blas A. Cuesta, Alberto Ros, María E. Gómez, Antonio Robles, and José F. Duato.
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks,
Proceedings of the 38th annual international symposium on Computer architecture (ISCA '11).
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