Date: Tue, 14 Jan 1997 20:43:31 GMT Server: Apache/1.0.3 Content-type: text/html Content-length: 5656 Last-modified: Wed, 20 Nov 1996 00:22:02 GMT B441/B541 Lab Syllabus for Fall, 1996

Digital Design B441/B541
Lab Syllabus for Fall, 1996


Contents


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Newsgroup

A newsgroup has been set up for this course: ac.csci.b441. It is recommended that you post all questions to this newsgroup. If you want to know the answer to a question, chances are someone else does, too. Also, if you know the answer to a question someone has posted, we encourage you to post your answer and discuss the possible solutions.

All of this, of course, assumes you are following the guidelines on academic honesty.


Format of the Lab

For the first nine weeks of the lab (except for the first lab), there will be an assignment due at the beginning of each lab. The assignment will typically consist of both written work and a working circuit on your logic engine. Since the PDP-8 is such a wiring intensive project, it will be divided into three parts with extended deadlines. In addition to the lab assignments, you will be given a laboratory exam relating to the PDP-8. This exam will come at the end of the semester and will test for practical, in-depth knowledge of your circuit.

Please note that, in general, you will be working in pairs. All written exercises are to be handed in individually and will be graded as individual work. You and your partner will co-operate on all circuits, however, and will be given a single grade for your circuitry. Because wiring experience will be shared, it is your responsibility to make sure you understand what wiring your partner has done and to make sure that you are doing your fair share. You may divide up the work however you and your partner prefer, but if we see that one of you is consistently not doing enough work, we may re-arrange the groups.


Laboratory Grading

The lab grade will be broken down in the following way:

Lab Info


Laboratory Schedule
Digital Design B441/B541
Fall '96

Week of
Manual Section
Topic
September 3 Lab 1 Introduction to laboratory equipment and procedures. Simulation.
September 10 | |
September 17 Lab 2 Mixed Logic
September 24 Lab 3 Three-state logic
| Lab 4 Programmable logic and PLDs
October 1 Lab 5 Synthesis of combinational elements -- muxes, encoders, comparators
October 8 Lab 6 An ALU
October 15 Lab 7 Sequential circuits -- counters
October 22 Lab 8 Register-transfer concepts
October 29 Lab 9 Building the PDP-8 data-path PALs
| Lab 10 Manual ASM control of the PDP-8
| Lab 11 Building the PDP-8 controller
November 5 | |
November 12 | |
November 19 | | (By this week, you should have completed the design and wiring of your PDP-8 processor, and should have installed and wired the supplied I/O interface.)
November 26
 
Thanksgiving Recess
December 3 Lab 12 Debugging and testing the PDP-8 processor
December 10 --- Final PDP-8 test and lab checkout
December 16
 
Finals Week -- no scheduled lab activity


dcw 8/27/96