Date: Mon, 11 Nov 1996 17:24:33 GMT Server: NCSA/1.5 Content-type: text/html Last-modified: Mon, 18 Mar 1996 14:36:23 GMT Content-length: 2837
UNIVERSITY OF WISCONSIN-MADISON
Computer Sciences Department | ||
CS 537
Spring 1996 | Bart Miller | |
Problem Set #2
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You are designing the memory mapping hardware for a new machine. The memory addressing will have segments that are paged. The machine has a 64-bit virtual address. Each process can have up to 64K (65536) segments, and page size is 64K bytes.
The segment tables (ST) and page tables (PT) are stored in main memory. ST's and PT's can start at any byte address. Each segment table entry (STE) points to a page table.
Each page table entry (PTE) points to a page in real memory. Each PTE will also have: a "read-enable" bit, a "write-enable" bit, and a bit that is set on each reference to the page.
This machine will support physical memories up to 64 gigabytes.
For each of the following page replacement algorithms, describe a case where the algorithm does a poor job in scheduling memory: LRU, LFU, FIFO.
Consider a demand paging system. We measure the various resource utilizations and see:
CPU utilization | 20% |
Paging disk | 99% |
Which of these (if any) should improve the CPU utilization? Why?