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Gaetano Borriello - Publications
Gaetano Borriello's publications of the last five years
Refereed Journals
- J. Carson, G. Borriello. A Testable CMOS Asynchronous Counter. IEEE Journal of Solid-State Circuits, Vol. SC-25, No. 4, August 1990.
- K. Bartlett, G. Borriello, S. Raju. Timing Optimization of Multi-Phase Sequential Logic. IEEE Transactions on Computer-Aided Design, Vol. 10, No. 1, January 1991.
- S. Bunton, G. Borriello. Practical Dictionary Management for Hardware Data Compression. Communications of the ACM, Vol. 35, No. 1, January 1992.
- P. Chou, E. Walkup, G. Borriello. Scheduling Issues in Hardware/Software Co-Synthesis. IEEE Micro, special issue on hardware/software co-design, August 1994.
- S. Hauck, S. Burns, G. Borriello, C. Ebeling. An FPGA for Implementing Asynchronous Circuits. IEEE Design and Test of Computers, special issue on asynchronous design, October 1994.
- H. Hulgaard, S. Burns, T. Amon, G. Borriello. An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE Transactions on Computers, accepted November 1994.
- H. Hulgaard, S. Burns, G. Borriello. Testing Asynchronous Circuits: A Survey. Integration: the VLSI journal, accepted January 1995.
- S. Hauck, S. Burns, G. Borriello, C. Ebeling. The Triptych FPGA Architecture. IEEE Transactions on VLSI Systems, accepted December 1994.
- N. Mckenzie, C. Ebeling, L. McMurchie, G. Borriello. Experiences with the UW MacTester in Computer Science and Engineering Education. IEEE Transactions on Education, accepted December 1994.
Patents
- A. Bell, R. Lyon, G. Borriello. Self-Calibrated Clock and Timing Signal Generator for MOS/VLSI Circuitry, U. S. Patent 4,494,021; January 15, 1985.
- G. Borriello, R. Lyon, A. Bell. Data and Clock Recovery System for Data Communication Controller, U.S. Patent 4,513,427; May 1, 1985.
- C. Ebeling, G. Borriello. Dynamically Reconfigurable Logic Array for Digital Logic Circuits, U.S. Patent 5,208,491; May 1993.
- S. Hauck, G. Borriello, S. Burns, C. Ebeling. Field-Programmable Gate Array for Synchronous and Asynchronous Operation, U.S. Patent 5,367,209, November 22, 1994.
Refereed Conferences
- S. Bunton, G. Borriello. Practical Dictionary Management for Hardware Data Compression. 6th MIT Conference on Advanced Research in VLSI, April 1990.
- C. Ebeling, G. Borriello. Making the Most of a Design Project. 3rd NSF Microelectronic System Education Conference, July 1990.
- L. McMurchie, C. Anderson, G. Borriello. Hybrid Compiled/Interpreted Simulation of MOS Circuits. 2nd European Design Automation Conference, February 1991.
- T. Amon, G. Borriello, C. Sequin. Operation/Event Graphs: A Design Representation for Timing Behavior. 10th IFIP International Conference on Computer Hardware Description Languages, April 1991.
- T. Amon, G. Borriello. Sizing Synchronization Queues: A Case Study in Higher Level Synthesis. 28th ACM/IEEE Design Automation Conference, June 1991.
- T. Amon, G. Borriello. OEsim: A Simulator for Timing Behavior. 28th ACM/IEEE Design Automation Conference, June 1991.
- C. Ebeling, G. Borriello. Establishing a Modern Digital Design Lab. 4th NSF Microelectronic System Education Conference, July 1991.
- G. Borriello, C. Ebeling, L. McMurchie. Teaching Design with a Next-Generation Schematics Capture System. 4th NSF Microelectronic System Education Conference, July 1991.
- D. Bouldin, G. Borriello, et. al.. Report on the Workshop on Microelectronics Systems Education in the 1990's. 4th NSF Microelectronic System Education Conference, July 1991.
- G. Borriello. Formalized Timing Diagrams. 3rd European Design Automation Conference, March 1992.
- C. Ebeling, G. Borriello, et. al.. Triptych: An FPGA Architecture with Integrated Logic and Routing. Brown/MIT Conference on Advanced Research in VLSI and Parallel Systems, March 1992.
- T. Amon, G. Borriello. An Approach to Symbolic Timing Verification. 29th ACM/IEEE Design Automation Conference, June 1992.
- P. Chou, R. Ortega, G. Borriello. Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems. IEEE/ACM International Conference on Computer-Aided Design, November 1992.
- H. Hulgaard, S. Burns, T. Amon, G. Borriello. An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. IEEE International Conference on Computer Design, October 1993. Best paper in CAD track.
- H. Hulgaard, S. Burns, T. Amon, G. Borriello. Practical Applications of an Efficient Time Separations of Events Algorithm. IEEE/ACM International Conference on Computer-Aided Design, November 1993.
- E. Walkup, G. Borriello. Interface Timing Verification with Application to Synthesis. 31st ACM/IEEE Design Automation Conference, June 1994.
- P. Chou, G. Borriello. Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems. 31st ACM/IEEE Design Automation Conference, June 1994.
- S. Hauck, G. Borriello, C. Ebeling. Mesh Routing Topologies for FPGA Arrays. IEEE International Conference on Computer Design, October 1994.
- H. Hulgaard, T. Amon, S. Burns, G. Borriello. Timing Analysis of Timed Event Graphs with Bounded Delays Using Algebraic Techniques. 33rd IEEE Conference on Decision and Control, December 1994.
- S. Hauck, G. Borriello. Logic Partition Orderings for Multi-FPGA Systems. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February 1995.
- S. Hauck, G. Borriello. An Evaluation of Bipartitioning Techniques. Chapel Hill Conference on Advanced Research in VLSI, March 1995.
- P. Chou, G. Borriello. Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems. 32nd ACM/IEEE Design Automation Conference, June 1995.
- P. Chou, R. Ortega, G. Borriello. The Chinook Hardware/Software Co-Synthesis System. 8th International Symposium on System Synthesis, September 1995, submitted March 1995.
Refereed Workshops
- T. Burks, K. Sakallah, K. Bartlett, G. Borriello. Performance Improvement through Optimal Clocking and Retiming. 3rd ACM International Workshop on Logic Synthesis (poster), May 1991.
- C. Ebeling, G. Borriello, S. Hauck, D. Song, E. Walkup. Triptych: A New Field-Programmable Gate Array Architecture. First IFIP International Workshop on Field Programmable Logic and Applications, Abingdon EE & CS Books, FPGAs, September 1991.
- E. Walkup, S. Hauck, G. Borriello, C. Ebeling. Routing-directed Placement for the Triptych FPGA. ACM International Workshop on Field Programmable Gate Arrays, February 1992.
- T. Amon, G. Borriello. An Approach to Symbolic Timing Verification. 2nd ACM/IEEE Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
- G. Borriello. A Model for Hardware/Software Co-Synthesis. IFIP International Workshop on Hardware/Software Co-Design, May 1992.
- S. Hauck, G. Borriello, S. Burns, C. Ebeling. Montage: An FPGA for Synchronous and Asynchronous Circuits. 2nd IFIP Workshop on Field-Programmable Logic and Applications, September 1992.
- P. Chou, R. Ortega, G. Borriello. Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems. IEEE International Workshop on Hardware/Software Co-Design, October 1992.
- G. Borriello, A. Sangiovanni-Vincentelli. Models for the Hardware/Software Co-Design of Embedded Controllers. IEEE International Workshop on Hardware/Software Co-Design, October 1992.
- S. Hassoun, G. Borriello. Improving Finite State Assignment for Two-Level Programmable Logic Devices. 4th ACM International Workshop on Logic Synthesis (poster), May 1993.
- E. Walkup, G. Borriello. Interface Timing Verification with Combined Max and Linear Constraints. 3rd ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, September 1993.
- H. Hulgaard, S. Burns, T. Amon, G. Borriello. Practical Applications of an Efficient Time Separation of Events Algorithm. 3rd ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, September 1993.
- P. Chou, G. Borriello. Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems. International Workshop on Hardware-Software Codesign, October 1993.
- E. Walkup, G. Borriello. Automatic Synthesis of Device Drivers for Hardware/Software Codesign. International Workshop on Hardware-Software Codesign, October 1993.
- S. Hauck, G. Borriello, C. Ebeling. Mesh Routing Topologies for FPGA Arrays. ACM International Workshop on Field Programmable Gate Arrays, February 1994.
- S. Hauck, G. Borriello, C. Ebeling. Springbok: A Rapid-Prototyping System for Board-Level Designs. ACM International Workshop on Field Programmable Gate Arrays (poster), February 1994.
- S. Hauck, G. Borriello. Pin Assignment for Multi-FPGA Systems. Workshop on FPGAs in Custom Computing Machines, April 1994.
- G. Borriello, D. Miles. Task Scheduling for Real-Time Multi-Processor Simulations. 11th IEEE Workshop on Real-Time Operating Systems and Software, May 1994.
Books and Book Chapters
- G. Borriello. Specification and Synthesis of Interface Logic. Invited chapter in High-Level VLSI Synthesis, R. Camposano and W. Wolf, editors, Kluwer Academic Publishers, 1991.
- G. Borriello, C. Ebeling, editors. Research On Integrated Systems - Proceedings of the 1993 Symposium, The MIT Press, 1993.
- R. Katz, G. Borriello, C. Ebeling. LogicWorks Instructor's Laboratory Manual. The Benjamin/Cummings Publishing Company, 1994.
gaetano@cs.washington.edu
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