Server: Netscape-Communications/1.1 Date: Wednesday, 15-Jan-97 01:16:21 GMT Last-modified: Sunday, 24-Nov-96 20:42:20 GMT Content-length: 5914 Content-type: text/html Joy Shetler's Home Page department issue photograph [Photo]

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Joy Shetler

Associate Professor
Computer Engineering Program
B.S., Electronic Engineering (Honors), Cal Poly, San Luis Obispo
M.S., Ph.D., Electrical And Computer Engineering, UC Santa Barbara

Office: 20-213
Phone: 805/756-2309
Email: jshetler@phoenix.csc.calpoly.edu


Biography:

Professor Shetler's research interests are in computer architecture and design. In June 1996, she received a CAREER grant from the National Science Foundation to establish an active research effort in microelectronic systems architecture that enhances the undergraduate curriculum in Computer Engineering, Computer Science and Electrical Engineering, and introduces students to new computer architectures, new technology and microelectronic systems.

The ideas developed by this research will be incorporated into the microprocessor and computer architecture curriculum. The focus of the research component is to devise and test Instruction Level Parallelism (ILP) techniques and mechanisms. Programmable Logic Devices, such as FPGAs, are used to implement rapid system prototyping of custom computer designs and are also used to implement custom components in reconfigurable architectures. Part of this project involves developing a rapid-prototyping platform.

Her industrial experience includes computer design at Burroughs Corp. (now UNISYS) for four years and at Trilogy Systems of Cupertino (now defunct). At Burroughs, she was a designer of the A9/A10 mainframe. While at Trilogy, she designed a multiprocessor cache coherency mechanism using Wafer Scale Integration (WSI).

Compcon

Dr. Shetler is currently serving on the steering committee for
Compcon 97.

Teaching Areas:

Dr. Shetler is teaching CPE 316 and CPE X436 for Fall Quarter, 1996. Only the information for those courses is valid. Information on other courses she has taught may not be up to date.

Digital Logic Design
CPE 219

This course covers introductory material on digital design techniques and theory.

Computer Architecture II
CPE 315

This course covers computer architecture and microprogramming. The emphasis is on the RTL (Register Transfer Level) design of RISC and CISC based architectures.

Computer Architecture III
CPE 316

This course covers computer architecture and interfacing techniques. The emphasis is on interfacing at the system bus level using asynchronous and synchronous protocols. Memory addressing strategies and memory mapped I/O are also covered. The lab associated with this course covers several team projects.

Digital Systems Design
CPE 319

This course covers the design of digital systems using combinational and sequential circuits. The course covers current implementation strategies including the use of PLDs and FPGAs.

Microprocessor Systems Design
CPE X436

This course covers microprocessor systems design.

Research Interests:

multithreaded processor designs
description
FPGA implementations
description
and more description

Recent & Current Master Theses students:

Recent Senior Projects Completed:

Senior Projects in Progress:

Please note that these are preliminary topics and may change slightly!

Accelerators:


  • Please send any constructive comments to Joy Shetler
  • copyRight © 1996 by CSC dept Cal Poly. All rights reserved, etc., etc.