Date: Wed, 15 Jan 1997 01:31:24 GMT Server: NCSA/1.4.2 Content-type: text/html Last-modified: Wed, 04 Sep 1996 19:19:54 GMT Content-length: 3679 Dissertation Abstract Click here to download the postscript version of this statement.

Abstract of Dissertation Prospectus

As device sizes continue to diminish, the chip gate-to-pin ratio increases, reducing chip testability. The strong effect of testability on production cost makes it imperative that it be well integrated into the VLSI design process. High-level synthesis automates the design process, allowing design alternatives to be explored more efficiently. The importance of testability necessitates exploration of test options during the design process as early as possible.

The increasing complexity of chip circuitry increases the cost of production by causing test time to rise, thereby reducing production throughput. For this reason, it is necessary to generate designs which deliver high fault coverage with low test time. Chip performance is a critical constraint for any high speed application area such as real time digital signal processing which is used in almost any multi-media application. The inclusion of testability into a design often causes a severe performance degradation. Since testability is also important for such designs, it is necessary to include testability with minimal impact on the chip performance. Low test time and reduced performance degradation must be achieved simultaneously during the design of a testable system.

The chief component of test time is the degree of allowable test concurrency between the testing of different parts of the chip. Two chip components may not be tested concurrently if the tests which examine the two components share hardware. In order to minimize test time, designs must be generated which allow tests to be defined which share hardware as little as possible. Performance is reduced when test registers are inserted into delay-critical paths of the design. Test registers must be inserted to ensure testability, while avoiding the delay critical paths of the circuit. Once a testable design has been generated, tests must be defined for that design which are parallelizable.

I will design a system which performs three tasks with the goal of test time minimization:

The work presented here will be applied to a wide range of Built-In Self-Test (BIST) methodologies. By altering the area overhead limitation, the designs produced by this system can range from fully centralized BIST, where all chip components are tested by the same test registers, to partially distributed BIST, where the degree of test register sharing is restricted.

The cost of chip testing has become a large fraction of chip production cost and the effect of test register insertion on performance is critical for any high speed application. The need for an integrated system which considers test time and performance reduction due to testability at the earliest stage of design is clear. Previous efforts to increase testability neither integrate the different levels of testable circuit design nor directly address the problem of minimizing test conflicts and performance degradation in a computationally efficient way.