Date: Mon, 02 Dec 1996 15:13:14 GMT Server: NCSA/1.4.2 Content-type: text/html CSE567 Summary

CSE 567: Principles of Digital Systems Design

Carl Ebeling, Fall 1996


Catalog Data: Principles of logic design, combinational and sequential circuits, structured design methods, digital system components, clocking methodologies, arithmetic circuits, memories, hardware description languages, logic and sequential synthesis, synthesis and simulation tools, implementation alternative, VLSI processor architecture, application-specific computation.

Prerequisites: A working knowledge of Boolean algebra and finite-state machines.
Familiarity with the department's computing environment: Unix/X

Course Goals: To provide in-depth understanding of digital systems and their design, including specification, synthesis, and implementation.

Facilities: You will be making extensive use of computer-aided design (CAD) tools for designing and implementing digital circuits. These tools are installed on the Sun workstations of the Northwest Laboratory for Integrated Systems (LIS). These are (mostly) located in Sieg 424 but are accessible from any X-terminal. You may find it advantageous to work in 424 where you can take advantage of manuals, reference texts and the knowledge of other students.

CAD Tools: CAD tools allow us to design and implement substantial hardware projects in a reasonable amount of time. They also provide hands-on experience with state-of-the-art design tools that incorporate the synthesis algorithms covered in class. These tools are introduced during the first half of the course as basic concepts are covered and then used heavily for the design project.

Assignments: There will be weekly assignments and labs during the first half of the quarter. They will give you experience with the concepts you will be using in the second half of the quarter for the design project and introduce you to the CAD tools.

Project: A substantial part of the course revolves around the team design of a large hardware systems project. Each team will design a complete project using schematics and Verilog for specification, Verilog-XL for simulation, the Synopsys tools for synthesis, and Xilinx FPGAs for implementation. Design projects in the past have included a Tetris player, an Ethernet interface, a cache monitor and DNA sequence matching. This quarter we will be designing hardware to implement an image processing algorithm. I haven't decided which algorithm yet, but examples include compression, filtering, edge detection, etc. We will be using a prototyping board containing several FPGAs and RAM that plugs into an Alpha workstation via a PCI bus. An image will be downloaded into the on-board RAM, transformed by the hardware into a compressed or filtered image, and then uploaded to the Alpha. The project will be well-defined, but students will be able to explore different options based on performance or cost as well as other possibilities such as color images or video.

Collaborative Learning: It is well known that students can learn a lot from each other given the chance. During the second week I will assign everyone into teams of three and four students. You will work together on the homework assignments and the project. Each member of the team will be responsible for the performance of all other team members; that is, the entire team must understand the solution and contribute to part of it. We will talk about how this works in more detail later.

Quizzes and Exams: There will be a short but challenging quiz every Friday at the end of class which will cover all material covered through that Wednesday. As compensation, there will be no mid-term exam. The final exam will be a two-hour comprehensive examination given at the regularly scheduled final exam time. Quizzes and the final exam will be open book and open notes.

Grading: The course grade will be roughly determined as follows:


ebeling@cs.washington.edu