Date: Tue, 14 Jan 1997 20:43:31 GMT Server: Apache/1.0.3 Content-type: text/html Content-length: 5656 Last-modified: Wed, 20 Nov 1996 00:22:02 GMT
All of this, of course, assumes you are following the guidelines on academic honesty.
Please note that, in general, you will be working in pairs. All written exercises are to be handed in individually and will be graded as individual work. You and your partner will co-operate on all circuits, however, and will be given a single grade for your circuitry. Because wiring experience will be shared, it is your responsibility to make sure you understand what wiring your partner has done and to make sure that you are doing your fair share. You may divide up the work however you and your partner prefer, but if we see that one of you is consistently not doing enough work, we may re-arrange the groups.
diglog
configuration file
Laboratory Schedule
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September 3 | Lab 1 | Introduction to laboratory equipment and procedures. Simulation. |
September 10 | | | | |
September 17 | Lab 2 | Mixed Logic |
September 24 | Lab 3 | Three-state logic |
| | Lab 4 | Programmable logic and PLDs |
October 1 | Lab 5 | Synthesis of combinational elements -- muxes, encoders, comparators |
October 8 | Lab 6 | An ALU |
October 15 | Lab 7 | Sequential circuits -- counters |
October 22 | Lab 8 | Register-transfer concepts |
October 29 | Lab 9 | Building the PDP-8 data-path PALs |
| | Lab 10 | Manual ASM control of the PDP-8 |
| | Lab 11 | Building the PDP-8 controller |
November 5 | | | | |
November 12 | | | | |
November 19 | | | | (By this week, you should have completed the design and wiring of your PDP-8 processor, and should have installed and wired the supplied I/O interface.) |
November 26 | Thanksgiving Recess | |
December 3 | Lab 12 | Debugging and testing the PDP-8 processor |
December 10 | --- | Final PDP-8 test and lab checkout |
December 16 | Finals Week -- no scheduled lab activity |