Date: Mon, 02 Dec 1996 15:11:36 GMT
Server: NCSA/1.4.2
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CSE467 Schedule
CSE467: Advanced Logic Design
Carl Ebeling, Spring 1996
List of topics and concepts covered this quarter:
- Truth tables and structured logic implementations
- PAL architectures and implementation issues
- PROM implementation of functions
- PLAs
- Multiplexors for functions
- Decoders and large decoder structures
- Tristate logic for multiplexing and busses
- TTL and CMOS logic families and interfacing issues
- Voltage levels and noise margins
- Current sink and drive capabilities of logic families
- Mixed logic notation, deMorgan's law
- Synchronous circuit design methodologies
- Timing characteristics of registers: setup/hold constraints and propagation delays
- Effects of clock skew
- Asynchronous inputs, "synchronizers" and metastability problems
- Finite state machine models: Mealy vs. Moore machines
- State diagrams and compiling to state tables and circuit implementation
- PLD implementation of state machines
- FGPA architectures: logic blocks and routing structures
- FPGA design methodologies and CAD tools: place and route
- 2-level logic minimization
- Multi-output function minimization
- Multilevel logic synthesis
- Algebraic and boolean division, kernel and cube factors
- Logic transformations including factoring and Shannon decomposition
- Techniques for mapping complex functions to PLDs
- Memory structures and control
- Static RAM architecture and timing
- Dynamic RAM architecture and timing
- Serial communication
- ABEL programming
- Oscilloscopes and Logic Analyzers
ebeling@cs.washington.edu