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Date: Wed, 13 Nov 1996 23:14:40 GMT
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Homework #3, Part II Solutions
Homework #3, Part II Solutions
Problem 6 A schematic of a 16-bit ALU. There
are several schematics which are part of this design, and they are listed
here.
16-bit AND unit
16-bit logical shift left (lsl) unit
2x1 16-bit mux
These next 2 components were created in Homework #2:
16-bit CLA adder
4x1 16-bit mux
Problem 7
A schematic of a Memory unit, plus its
component part schematics:
memory control unit
RAM module
Problem 8
Implementing MYCALC requires you to use the ALU and memory module that you
created in the previous two design questions, plus you must make a program
counter which can count up by 1. Beyond this, the rest of the design is a
finite state machine which must be able to cycle through the instructions
in the memory (which you pre-loaded into the RAM) and execute them. The
control for MYCALC must be able to synchronize the actions of the memory
and the program counter. The ALU is purely combinational, so it deosn't
really require synchronization. However, it would be a nice feature if
the output of MYCALC (i.e., the output of the ALU) was tristated off if
the value was invalid (before the first instruction is executed).
To prove that MYCALC works correctly, it must be simulated with a wide
range of input sequences that exercises all of MYCALC's capabilities. The
simulation results must illustrate that every part of it works - hiding
something that doesn't work will not suffice!!
Course Account ece552