Date: Mon, 25 Nov 1996 23:58:31 GMT Server: NCSA/1.5.1 Last-modified: Fri, 08 Nov 1996 18:40:34 GMT Content-type: text/html Content-length: 6969 Memoria

The Memoria Project

Principal Investigators:

Current Graduate Students:

Current Undergraduate Students:

Description:

The goals of the Memoria project are to use source-level analysis to improve the memory performance of advanced microprocessors. Current research efforts include algorithms for combining software prefetching and unroll-and-jam, automatic optimization of linear algebra codes, optimizing loop order for cache performance and using high-level analysis in low-level code generation. This project is intimately entwined with the Rocket project.

Publications:

S. Carr, "Combining Optimization for Cache and Instruction-Level Parallelism", To appear in PACT '96, Boston, MA. Michigan Technological University, Department of Computer Science, Technical Report TR95-06.

K. McKinley, S. Carr and C-W. Tseng, "Improving Data Locality with Loop Transformations", To appear in ACM Transaction on Programming Languages and Systems. Michigan Technological University, Department of Computer Science, Technical Report TR95-09.

S. Carr, C. Ding and P. Sweany, "Improving Software Pipelining with Unroll-and-Jam", In Proceedings of the 29th Annual Hawaii International Conference on System Sciences.

S. Carr and R.B. Lehoucq , "A Compiler Blockable Algorithm for QR Decomposition" , Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing.

S. Carr, K. McKinley and C-W. Tseng, "Compiler Optimizations for Improving Data Locality", Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems.

S. Carr and K. Kennedy, "Improving the Ratio of Memory Operations to Floating-Point Operations in Loops", ACM Transactions on Programming Languages and Systems, November 1994.

S. Carr and K. Kennedy, "Scalar Replacement in the Presence of Conditional Control Flow", Software -- Practice & Experience 24(1), January 1994.

S. Carr and K. Kennedy, "Compiler Blockability of Numerical Algorithms", Proceedings of Supercomputing '92.

D. Callahan, S. Carr and K. Kennedy, "Improving Register Allocation for Subscripted for Subscripted", Proceedings of the SIGPLAN 1990 Conference on Programming Language Design and Implementation.

Invited Publications:

S. Carr and K. Kennedy, "Compiling Scientific Code for Complex Memory Hierarchies", Proceedings of 24th Hawaii International Conference on System Sciences.

S. Carr and K. Kennedy, "Blocking Linear Algebra Codes for Memory Hierarchies", Proceedings of 4th SIAM Conference on Parallel Processing for Scientific Computing.

Technical Reports:

S. Carr and Q. Wu, "Scalar Replacment and the Law of Diminishing Returns", Michigan Technological University, Department of Computer Science, Technical Report TR96-04. Submitted to the Journal of Programming Languages.

S. Carr and R.B. Lehoucq , "Compiler Blockability of Dense Matrix Factorizations", Michigan Technological University, Department of Computer Science, Technical Report TR95-08. Submitted to ACM Transactions on Mathematical Software.

S. Carr and Q. Wu, "An Analysis of Unroll-and-Jam on the HP 715/50", Michigan Technological University, Department of Computer Science, Technical Report TR95-05.

S. Carr and Q. Wu. "An Analysis of Loop Permutation on the HP PA-RISC", Michigan Technological University, Department of Computer Science, Technical Report TR95-03.

S. Carr and Q. Wu, "The Performance of Scalar Replacement on the HP 715/50", Michigan Technological University, Department of Computer Science, Technical Report TR95-02.

Research Grants:

"Hiding the Latency Between Level-1 and Level-2 Cache on the Alpha 21164", Digital Equipment Corporation, 1995-1997, $83,500.

"Improving the Cache Performance of Scientific Applications", NSF CCR-9409341, 1994-1997, $82,584 with $109,899 in matching funds.

"Improving the Memory Performance of the HP PA-RISC", Hewlett-Packard Company, 1994-1995, $56,000.

"Cache-Conscious Loop Unrollilng", Hewlett-Packard Company, 1993, $41,000.

PhD Dissertations:

S. Carr. "Memory Hierarchy Management" , Rice University, Department of Computer Science, September 1992.

Masters' Theses:

Y. Guan. "Unroll-and-Jam Guided by a Linear-Algebra-Based Memory-Reuse Model", Michigan Technological University, Department of Computer Science, December 1995.

C. Ding. "Improving Software Pipelining with Unroll-and-Jam and Memory-Reuse Analysis", Michigan Technological University, Department of Computer Science, June 1996.