Date: Mon, 02 Dec 1996 15:10:53 GMT Server: NCSA/1.4.2 Content-type: text/html CSE567 Homework Assignment #3

CSE 567: Principles of Digital Systems Design

Carl Ebeling, Fall 1996


Homework 3

Distributed: Friday Oct. 18 - Due Monday Oct. 28, in class


For problems involving Verilog code, hand in your code and your simulation log (or at least part of it if it's really long). For the synthesis problems, hand in a printout of the circuit schematic generated.

  1. Generate all the kernels of the following expression using the rectangle covering method:

     f = ace + acg + bce + bcg + ade + adg + bde + bdg
    
  2. Minimize the following expression using multi-level logic. The cost of this expression implemented directly as gates is 7 gates and 30 inputs (literals). Minimize this circuit in terms of literals.

    Use the rectangle method to find interesting kernel and cube divisors. Remember that as each time you factor the function, you create a new expression and new rectangle covering table.

    X = adeg + cdeg + afg + hi + bdeg + cfg + bfg
    
  3. Look at the two Verilog implementations of a comparator in /projects/lis/cse567/verilog/examples/comparator/ and simulate each using the verilog simulator. ("verilog.exe compare_TB.v" will do the trick)
  4. Use the comparator Verilog module to construct a MIN/MAX circuit. This MIN/MAX module has two 4-bit inputs, A and B, and two 4-bit outputs, Large and Small, where Large is the larger of A and B and Small is the smaller. Simulate your circuit to validate its behavior.
  5. Use the MIN/MAX circuit to implement a sorting network that sorts four numbers. Simulate and validate its behavior.
  6. Synthesize the circuit for the expression in problem 2 using Synopsys. (Directions for synthesis) Does Synopsys give you the same circuit you found?
  7. Synthesize the 4-bit comparator module in compare2.v. Try different opimization settings, including the defaults. What's the "best" circuit you can come up with?
  8. Try synthesizing a 32-bit comparator using Synopsys. How well can you guide the results by fiddling different timing and cost constraints?

ebeling@cs.washington.edu