JOURNAL OF ELECTRONIC TESTING Theory and Applications (JETTA) For aims and Scope, Submission of papers, information and order information see file jett.inf CONTENTS VOLUME 4 VOLUME 4, ISSUE 1, February 1993 SPECIAL ISSUE ON SYNTHESIS, TEST AND VERIFICATION Guest editors: Srinivas Devadas & Petra Michel - Editorial by Vishwani Agrawal - Guest Editorial by S. Devadas and P.Michel - New Editorial Board Members - List of Reviewers - An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques by G. Cabodi, P. Camurati, F. Corno, P. Prinetto, and M. Sonza Reorda - Synchronizing Sequences and Symbolic Traversal Techniques in Test Generation by H. Cho, S.-W. Jeong, F. Somenzi, and C. Pixley - Functional Versus Random TEst Generation for Sequential Circuits by M. Karam, and G. Saucier - Testability Analysis in High Level Data Path Synthesis by J. Steensma, W. Geurts, F. Catthoor, H. De Man - Finite State Machine Synthesis with Fault Tolerant Test Function by S.T. Chakradhar, S. Kanjilal, and V.D. Agrawal - Generating a Family of Testable Designs Using the BILBO Methodology by S.P. Lin, C.A. Njinda, and M.A. Breuer - A Synthesis-Based Test Generation and Compaction Algorithm for Multifaults by S. Devadas, K. Keutzer, and S. Malik - Enhancing On-Line Testability during Synthesis by B. Eschermann - CALL FOR PAPERS: SPECIAL ISSUE ON TESTING OF MULTI-MEGABIT MEMORIES VOLUME 4, ISSUE 2, May 1993 - Editorial by Agrawal Fault Models - Logical Redundancies in Irredundant Combinational Circuits by S. Chakraborty, D.K. Das, and B.B. Bhattacharya Delay Faults - Delay Fault Simulation of Sequential Circuits by K. Hirabayashi Test Generation - An Architectural Level Test Generator Based on Nonlinear Equation Solving by J. Lee, and J.H. Patel Built-In Self Test - Aliasing Properties of Circular MISRs by G. Edirisooriya, and J.P. Robinson Boundary Scan Applications - Test Program Synthesis for Modules and Chips Having Boundary Scan by J.-C. Lien, and M.A. Breuer - Efficient Board Interconnect Testing Using the Split Boundary Scan Register by N.S. Haider, and N. Kanopoulos JETTA LETTER - On the Exact Ordered Binary Decision Diagram Size of Totally Symmetric Functions by M. Heap VOLUME 4, ISSUE 3, August 1993 - Editorial by V.D. Agrawal FAULT TOLERANT AND TESTABLE DESIGN - Testability and Test Generation for Majority Voting Fault- Tolerant Circuits by Stroud/Barbour - On the Testability of Array Structures for FFT Computation by Lombardi/Muzio SWITCH-LEVEL TESTING - A Neural Netowrk Algorithm for Testing Stuck-Open Faults in CMOS Combinational Circuits by Z.Zhang/R.D. McLeod/W. Pedrycz TEST GENERATION - On the Generation of Test Patterns for Multiple Faults by Karkouri/Aboulhamid/Cerny FAULT SIMULATION - A Fault Simulation Method: Parallel Pattern Critical Path Tracing by So/Kime BUILT-IN SELF-TEST - Self-testing and Self-checking Combinatorial Circuits with Weakly Independent Outputs by Sogomonjan/Goessel JETTA LETTERS - Testing of Multi-Output Circuits by means of Signature Analyzer by Stolov - The Optimistic Update Theorem for Path Delay Testing in Sequential Circuits by Bose/Agrawal/Agrawal VOLUME 4, ISSUE 4, November 1993 JOINT SPECIAL ISSUE ON ANALOG DESIGN-FOR-TEST Guest Editor: Mani Soma Also published in Analog Integrated Circuits and Signal Processing, Volume 4, No. 3, Kluwer Academic Publishers -Editorial by Vishwani Agrawal -Introduction by Mani Soma -Improving the Testability of Switched-Capacitor Filters by J.L. Huertas, A. Rueda and D. Vazquez -Enchancing Design-for-Test for Active Analog Filters by Using CLP (R) by Franc Novak, Igor Mozetic, Marina Santo-Zarnik and Anton Baisizzo -Multiple Fault Analog Circuit Testing by Sensitivity Analysis by Naim Ben Hamida and Bozena Kaminska -DRAFTS: DiscRetized Analog Circuit Fault Simulator by Naveena Nagi, Abhijit Chatterjee and Jacob A. Abraham -A Hierarchical Analog Test Bus Framework for Testing Mixed- Signal Integrated Circuits and Printed Circuit Boards by Nai-Chi Lee -A Structure for Interconnect Testing on Mixed-Signal Boards by B.R. Wilkins and B.S. Suparjo CONTENTS VOLUME 3 VOLUME 3, ISSUE 1, February 1992 - Editorial - New Editorial Board Members - List of Reviewers - Built-In Self Test Aliasing Probability Transients J.P. Robinson Discrete Logarithms: A Parallel Pseudorandom Pattern Generator Analysis Method P.H. Bardell Counter-Based Compaction: An Analysis for BIST S. Pilarski and K. Weibe Parity Bit Calculation and Test Signal Compaction for BIST Applications S. Park and S.B. Akers - Self-Checking Design The OR-k Method for On-Line Checking of Programmable Logic Arrays D.M. Marcynuk and D.M. Miller - Fault Simulation MIT-SIM: A Mixed-Level Transition Fault Simulator Based on Parallel Patterns C.L. Lee, C.P. Wu, W.Z. Shen, T.S. Hwang and S. Hwang Fault Simulation on Massively Parallel SIMD Machines: Algorithms, Implementations and Results V. Narayanan and V. Pitchumani - Defects and Yield Test Quality of Hierarchical Defect-Tolerant Integrated Circuits C. Thibeault, Y. Savaria, and J.-L. Houle VOLUME 3, ISSUE 2, May 1992 - Editorial - Fault Simulation The Comparative and Concurrent Simulation of Discrete-Event Experiments E. Ulrich, K.P. Lentz, J. Arabian, M. Gustin, V.D. Agrawal and P.L. Montessoro - Delay Testing AC Strength of a Pattern Generator J. Savir and R. Berry - Design for Testability A Test Methodology for Finite State Machines Using Partial Scan Design H.B. Min and W.A. Rogers Constant Testability of Combinatorial Cellular Tree Structures F. Lombardi and D. Sciuto On The Design of Random Pattern Testable PLA Based on Weighted Random Pattern Testing D.S. Ha and S.M. Reddy - Boundary Scan An Implicity Testable Boundary Scan TAP Controller B. Eschermann - Jetta Letters Multiple Fault Detection in Two-Level Multi-Output Circuits J. Jacob and V.D. Agrawal Primitive Polynomials of Degree 301 through 500 P.H. Bardell VOLUME 3, ISSUE 3, August 1992 - Editorial - Analog Circuit Testing A Decomposition Approach for Testing Large Analog Networks J.A. Starzyk and H. Dai - Fault Modeling Dynamic Effects in the Detection of Bridging Faults in CMOS ICs M. Favalli, P. Olivo, and B. Ricco Testability Analysis and Fault Modeling of BiCMOS Circuits D. Al-Khalili, C. Rozon, and B. Stewart - Sequential Machine Testing A Model for Sequential Machine Testing and Diagnosis J.A. Brzozowski and H. Jurgensen - Memory Testing An Efficient Design of Embedded Memories and their Testability Analysis Using Markov Chains P. Mazumder and J.H. Patel Near-Optimal Tests for Classes of Write-Triggered Coupling Faults in RAMs B.F. Cockburn and J.A. Brzozowski Testing of Static Random Access Memories by Monitoring Dynamic Power Supply Current S.-T. Su and R.Z. Makki - Erratum - Call for Papers Special Issue on Test Economics - Letters VOLUME 3, ISSUE 4, December 1992 SPECIAL ISSUE ON IDDQ TESTING OF VLSI CIRCUITS - Editorial by V.D. Agrawal - Introduction by R.K. Gulati and C.F. Hawkins - Iddq Testing: A Review by J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao - Iddq Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metrics by P.C. Maxwell and R.C. Aiken - Iddq Testing in CMOS Digital Asic's by R. Perry - Diagnosis of Leakage Faults with Iddq by Aitken - Reliability Benefits of Iddq by S.D. McEuen - Quiescent Current Analysis and Experimentation of Defective CMOS Circuits by J.A. Segura, V.H. Champac, R. Rodriguez- Montanes, J. Figueras and J.A. Rubio - QUIETEST: A Methodology for Selecting Iddq Test Vectors by W. Mao and R.K. Gulati - Generation and Evaluation of Current and Logic Tests for Switch-Level Sequential Circuits by C.-H. Cheng and J.A. Abraham - Diagnosis of Leakage Faults with Iddq by R.C. Aitken - Algorithms for Iddq Measurement Based Diagnosis of Bridging Faults by S. Chakravarty and M. Liu - Proportional BIC Sensor for Current Testing by J. Ruis and J. Figueras - Design of ICs Applying Built-In Current Testing by W. Maly and M. Patyra CONTENTS VOLUME 2 VOLUME 2, ISSUE 1, March 1991 - Editorial V.D. Agrawal - Guest Editorial R.G. Bennetts - New Editorial Board Members - List of Reviewers - IEEE Standard 1149.1-1990 on Boundary Scan: History, Literature Survey, and Current Status R.J. Bennetts and A. Osseyran - An Introduction to the Boundary-Scan Standard: ANSI/IEEE Std 1149.1 C.M. Maunder and R.E. Tulloss - A Language for Describing Boundary-Scan Devices K. P. Parker and S. Oresjo - Boundary Scan Test, Test Methodology and Fault Modeling F. de Jong, J.S. Matos and J.M. Ferreira - ATPG and Diagnostics for Boards Implementing Boundary Scan D. Sterba, A. Halliday and D. McClean - Scan Test Architectures for Digital Board Testers M.L. Fichtenbaum and G.D. Robinson - Features of a Scan and Clock Resource Chip for Providing Access to Board-Level Test Functions B.I. Dervisoglu - An Optimal Scheduling Algorithm for Testing Interconnect Using Boundary Scan J.-C. Lien and M.A. Breuer VOLUME 2, ISSUE 3, August 1991 - Editorial V.D. Agrawal - Probabilistic Testability Combined Probabilistic Testability Calculation and Compact Test Generation for PLAs B. Reppen and E.J. Aas - Fault Modeling Fault Modeling and Fault Equivalence in CMOS Technology M. -L. Flottes, C. Landrault and S. Pravossoudovitch Exact Ordered Binary Decision Diagram Size when Representing Classes of Symmetric Functions D.E. Ross, K.M. Butler and M.R. Mercer -Design for Testability A Methodology for the Design of SFS/SCD Circuits for a Class of Unordered Codes S. Pagey, S.D. Sherlekar and G. Venkatesh - Built-in Self-Test Constrained Parity Testing P.K. Lui and J.C. Muzio - Fault-Tolerant Semiconductor Memories Redundancy Effect on Yield of Binary Tree RAMs B. Ciciani - JETTA Letter Comments on "Optimizing Error Masking in BIST by Output Data Modification" R. Kh. Latypov VOLUME 2, ISSUE 4, November 1991 - Editorial V.D. Agrawal - Probabilistic Testability Bounding Fault Detection Probabilities in Combinational Circuits G. Markowsky - Test Complexity Measures Bounds on the Sizes of Irredundant Test Sets and Sequences for Combinational Logic Networks W.H. Debany, Jr. and C.R.P. Hartmann The Minimum Test Set Problem for Circuits with Nonreconvergent Fanout I. Pomeranz and Z. Kohavi - Test Generation and Design for Testability Test Generation, Design-for-Testability and Built-In Self-Test for Arithmetic Units Based on Graph Labeling A. Chatterjee and J.A. Abraham - Built-In Self-Test Analysis of Hamming Count Compaction Scheme W.-B. Jone and A. Gleason - Electron Beam Testing Model-Based Reasoning for Electron-Beam Debugging of VLSI Circuits M. Marzouki - JETTA Letter Checkpoints in Irredundant Two-Level Combinational Circuits J.E. Chen, C.L. Lee, and W.Z. Shen - Call for Papers Special Issue on CMOS I DDQ Testing CONTENTS VOLUME 1 VOLUME 1, ISSUE 1, February 1990 - Editorial - List of Reviewers - Fault Simulation Differential Fault Simulation for Sequential Circuits W.-T. Cheng and M.-L. Yu - Synthesis for Testability Redundancies and Don't Cares in Sequential Logic Synthesis S. Devadas, H.-K.T. Ma and A.R. Newton - Fault Tolerance and Yield Improvement Fault-Tolerance in Balanced Sorting Networks J. Sun, J. Gecsei and E. Cerny Yield Enchancement and Manufacturing Throughput of Redundant Memories by Repairability/Unrepairability Detection Y.-N. Shen and F. Lombardi - Built-In Self Test Optimization Error Masking in BIST by Output Data Modification Y. Zorian and V.K. Agarwal Design Considerations for Parallel Pseudorandom Pattern Generators P.H. Bardell - Editorial Board VOLUME 1, ISSUE 2, May 1990 - Editorial - Test Generation A Hierarchical Test Generation Methodology for Digital Circuits D. Bhattacharya and J. P. Hayes Search Strategy Switching: Cost Model and an Analysis of Backtracking H.B. Min and W.A. Rogers - Fault Simulation Hierarchical Multi-level Fault Simulation of Large Systems D.G. Saab, R.B. Mueller-Thuns, D. Blaauw, J.T. Bahmeh, J.A. Abraham - Memory Testing Detection of Coupling Faults in RAMs J.A. Brzozowski and B.F. Cockburn - Design for Testability An Analytical Approach to the Partial Scan Problem A. Kunzmann and J.J. Wunderlich - JETTA Letters Multiple-Output Parity BIT Signature for Exhaustive Testing W.B. Jone and S.R. Das VOLUME 1, ISSUE 3, October 1990 - Editorial V.D. Agrawal - Test Generation Extended Selection of Switching Target Faults in CONT Algorithm for Test Generation Y. Takamatsu and K. Kinoshita Robust Tests for Parity Trees S. Kundu and S.M. Reddy - Systems Diagnosis Distributed Diagnosis for Homogeneous Systems Y.-H. Choi - Built-in Self-Test Feedback-Testing by Using Multiple Input Signature Registers M. Rudolph - Synthesis for Testability Finite State Machine Synthesis with Embedded Test Function V.D. Agrawal and K.-T. Cheng - JETTA Letters Exact Probabilistic Testability Measures for Multi-Output Circuits P. Camurati, P. Prinetto, and M. Sonza Reorda Probabilistic Fault Grading Based on Activation Checking and Observability Analysis M. Nakazawa, S. Nitta, and K. Hirabayashi VOLUME 1, ISSUE 4, January 1991 - Editorial V.D. Agrawal - Probabilistic Testability The Probability of Error Detection in Sequential Circuits Using Random Test Vectors A.A. Ismaeel and M.A. Breuer - Fault Modeling Shorts in Self-Check Circuits N. Nicolaidis A Characterization of Robust Test-Pairs for Stuck-Open Faults S. Chakravarty - Design for Testability A Methodology for Testability Enhancement at Layout Level J.P. Tiexeira, I.C. Teixeira, C.F.B. Almeida, F.M. Concalves and J. Concalves - JETTA Letter Ring-like Testing of Digital Circuits I.P. Litikov