To simulate the performance of our applications, we first use the SUIF compiler to generate fully-functional MIPS object code with prefetching. Since the MIPS-I instruction set does not contain a prefetch instruction, our compiler encodes prefetches as loads to R0. This encoding is attractive for the purpose of simulation since it has the same addressing mode (base-plus-offset) and register usage (a single source register and no real target register) as an actual prefetch instruction, and therefore produces accurate instruction counts.
The performance of the resulting object code is simulated by using the MIPS pixie utility  to generate an instrumented version of the code, and then piping the resulting trace into our detailed cache simulator. Our simulator makes the simplifying assumption that all instructions execute in a single cycle and that all instructions hit in the primary instruction cache. Otherwise, the cache tag state and all forms of contention described in Section (e.g., primary cache tags, memory bus) are modeled in detail.