The success of software-controlled prefetching relies on the combined support of both hardware and software. While part of the attractiveness of this technique is the simplicity of the hardware support, that support is nonetheless crucial. This chapter addresses these architectural issues associated with software-controlled prefetching.
We begin in Section with a detailed examination of the basic architectural support that was assumed in Chapters and . During this examination, we will justify each aspect of the architecture, and will quantify the relevant tradeoffs whenever possible. Next, we look to the future, considering additional ways to improve prefetching performance which involve some amount of architectural support. For example, we will look at using dynamic information to improve the analysis of what to prefetch, and increasing cache associativity to make prefetches more effective. Finally, in Section , we compare software-controlled prefetching with other latency-hiding techniques that require hardware support, such as relaxed consistency models and multithreading.