| Research - Tim Callahan |
I'm currently a systems-track faculty member at CMU: the Phoenix Group with Seth Goldstein --- spatial dataflow computing -- applying my previous experience now towards compilation for application-specific hardware and asynchronous reconfigurable platforms. This approach has been shown to give great energy-delay benefits over superscalar implementations, typically by two orders of magnitude. Is this due to the asynchronous circuits (eliminating the clock tree energy), or due to elimination of per-cycle instruction fetch, decode, and issue (complicated greatly in superscalar implementations)? We are in the process of teasing apart the components now.
With the great reduction of fetch/decode/issue energy, we now actually care about the energy for the execution of speculative operations. On a superscalar processor, doing an extra addition or two in a loop was completely in the noise -- not so any more. So my main direction now is evaluating how to best manage speculation in a low-energy, spatial computing situation. This involves both compile-time and dynamic approaches.
While at Berkeley I worked in the BRASS Research Group, developing compiler/CAD technology for reconfigurable platforms, and in particular, for the Garp chip, which integrates a rapidly reconfigurable array with a standard microprocessor (crude picture of Garp). My work encompassed all aspects of compiling ANSI C to the Garp chip, from automatic partitioning between SW and reconfigurable HW, all the way down to rapid timing-driven mapping and placement of modules on the reconfigurable array.This work has been used by Synopsys as the basis for the Nimble Compiler project. There's an article in EE Times describing it, and a bit more here.
I've also worked in the areas of parallel programming (vector, shared memory, and distributed memory); multiprocessor networks; DSP algorithms & coding; and protein/drug simulation (molecular dynamics), analysis (see here) , & visualization; see below for pointers to old publications and software.
Here's an unpolished version of my CV.
Here's my list of interesting companies.
Miscellaneous SUIF 1.3.0.5 passses
| PhD Thesis |
``Automatic Compilation of C for Hybrid Recofigurable Architectures.''
Timothy John Callahan
Ph.D. Thesis, 2002.
| Selected Publications |
`` Tartan: Evaluating Spatial Computation for Whole Program Execution'', Mahim Mishra, Timothy J. Callahan, Tiberiu Chelcea, Girish Venkataramani, Mihai Budiu and Seth C. Goldstein. International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), Oct 21-25, 2006, San Jose, CA.``The Garp Architecture and C Compiler'',
Timothy J. Callahan, John Hauser, and John Wawrzynek. IEEE Computer April 2000.
(IEEE Computer Society members can download the PDF from here.)``Adapting Software Pipelining for Reconfigurable Computing'',
Timothy J. Callahan and John Wawrzynek. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2000.``Hardware-Software Co-Design of Embedded Reconfigurable Architectures'',
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph E. Harr, Uday Kurkure, and Jon Stockwood. Design Automation Conference (DAC) 2000. Link to PDF.``Instruction Level Parallelism for Reconfigurable Computing'', Timothy J. Callahan and John Wawrzynek. 8th International Workshop on Field-Programmable Logic and Applications (FPL'98) , Tallinn, Estonia, August 31-September 3 1998. Published in LNCS-1482, Reiner W. Hartenstein and Andres Keevallik eds., Springer-Verlag.
``Fast Module Mapping and Placement for Datapaths in FPGAs'', Timothy J. Callahan, Philip Chong, André DeHon, and John Wawrzynek, Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Prog rammable Gate Arrays (FPGA '98, February 22-24, 1998), 10 pages.
``NIFDY: A Low Overhead, High Throughput Network Interface'' (Abstract), Tim Callahan and Seth Copen Goldstein. Proceedings of the 22nd International Symposium on Computer Architecture (ISCA), Santa Margherita Ligure, Italy, June 1995.
``Network Interface Specification for the T1 Microprocessor'' (Abstract), Timothy J. Callahan. Computer Science Division Technical Report CSD-94-823, U.C. Berkeley, May 1994.
``MD Display: An Interactive Graphics Program for Visualization of Molecular Dynamics Trajectories'', Timothy J. Callahan, Eric Swanson, and Terry P. Lybrand. J. Molecular Graphics, Vol. 14, No. 1, Feb. 1996, pp.39-41
``A Simple Profiling System for SUIF'', Tim Callahan and John Wawrzynek. The First SUIF Compiler Workshop, Stanford University, January 1996.
| Software |
Miscellaneous SUIF 1.3.0.5 passses (including SUIF procedure inlining pass)
The TCOVSUIF page -- OBSOLETE -- contains links to the current distribution, the README files from the distribution, and the paper and slides from the SUIF Workshop. The distribution includes a utility "bb2d", which translates the profiling output of programs compiled with "gcc -a -ggdb" to a format that can be used with the SunOS/Solaris utility tcov.
The MD Display software is available through QCPE, package #623.
Oxford Molecular also distributes it along with the AMBER molecular modeling package from UCSF (although MD Display is not an official AMBER program).
| Posters, Slides etc. |
- "Kernel Formation in Garpcc", FCCM'03, abstract: postscript.
- Slides from the demo at FCCM'99:
garpcc_demo.ps .gz (66kB), garpcc_demo.ps. Z (132kB), garpcc_demo.ps (4 98kB)
- Full-sized slides and 6-to-a-page slides from the August 21 1996 BRASS/IRAM retreat.
- Full-sized slides and 4-to-a-page slides from the January 13-15 1997 BRASS/IRAM retreat.
- Preliminary poster and extended abstract for Gama, the Garp Mapper (FCCM'97).
- HTMLized slides from the July 21-23 1997 BRASS/IRAM retreat.
| Tim Callahan | timothyc@cs.berkeley.edu |