Systems Seminar: Prof. Yale Patt, Electrical Engineering and Computer Science Department, University of Michigan, Ann Arbor

High Performance Microprocessor Implementation: The Next Set of Challenges, and a Few Ideas

Abstract

There seems to be no end to the higher and higher performance expected of future generations of microprocessors. By the year 2005, process technologists promise one billion transistors on a single chip, and we are expected to harness them in behalf of higher performance. Performance is always about delivering instruction bandwidth to the core, and then consuming that bandwidth. That means very wide issue machines, combined with what it takes to support them. In this talk, we will discuss the three basic challenges to delivering instuction bandwidth (ICache misses, packet breaks, and conditional branches), and our latest activities to improve what we can do about each. We will also take a look at the back end of the processor, what it takes to consume that instruction bandwidth.

Speaker Bio

Yale Patt is Professor of EECS at Michigan, where he enjoys equally teaching freshman and graduate students, and directing the research of nine PhD students in High Performance Computer Implementation. He was recently named a Thurnau Professor at the University of Michigan. He has been blessed with many other honors in life thus far, including receiving the 1996 IEEE/ACM Eckert-Mauchly Award, receiving the 1995 IEEE Piore Medal, signing Greg Ganger's PhD dissertation, and having both Dave Nagle and Garth Gibson in class. He has also done some work in branch prediction.