Systems Seminar: Prof. Mark Horowitz, EE and CS Departments, Stanford University

The Future of Wires

Abstract

At first glance, the future of wires in integrated circuit technologies looks grim. Even projections with copper interconnections and low-k dielectrics show that wire delay for a fixed length wire will increase at a rate that is greater than linear with scaling factor. This has led to a number of papers which have predicted the demise of conventional wires and the need for new interconnection methods.

This talk examines wire scaling and the capabilities of future wiring systems in more detail to try to better understand the constraints of these systems. The results are a little surprising. If an existing circuit is scaled to a new technology, the relative change in the speed of wires versus the speed of gates is modest. Depending on the assumptions on transistor performance under scaling, low-k dielectrics, and higher aspect ratio wires, the ratio is close to one. Thus the performance of today's IP cores should continue to improve with technology scaling. The key part of this scenario is the length of the wires measured in gate pitches has remained constant, so the length in microns has scaled. Designers will not need to repartition current designs into smaller blocks, but wire performance does not improve enough to make fast global communication on wires in a billion-transistor chip feasible.

Speaker Bio

Mark Horowitz is the Yahoo Founder's Professor of Electrical Engineering and Computer Science at Stanford University. He received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Dr. Horowitz is the recipient of a 1985 Presidential Young Investigator Award, and an IBM Faculty development award, as well as the 1993 best paper award at the International Solid State Circuits Conference. Dr Horowitz's research area is in digital system design, and he has lead a number of processor designs including MIPS-X, one of the first processors to include an on-chip instruction cache, TORCH, a statically-scheduled, superscalar processor that supported speculative execultion, and FLASH, a flexible DSM machine. He has also worked in a number of other chip design areas including high-speed and low-power memory design, high-bandwidth interfaces, and fast floating point. In 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology. His current research includes multiprocessor design, low power circuits, memory design, and high-speed links.