Systems Seminar: Dr. Pradip Bose, IBM T.J. Watson Research Center

Performance Evaluation and Validation of Microprocessors: Current Challenges

Abstract

In this talk, we provide an overview of the current challenges in pre-silicon evaluation and validation of processors. This is based largely on the speaker's own perspective, developed over many years of experience as a performance architect in IBM's PowerPC design projects.

The design methodology used in modern microprocessor development projects is rather complex. It requires modelling at various levels of abstraction. Prior to detailed circuit and physical design stages, such modelling ranges from early-stage performance models to detailed register-transfer-level (RTL) models. There are several problems with the current methodology as we try to scale up our toolsets to meet future needs. Perhaps the biggest challenge we face is the so-called "verification bottleneck". A major focus of this talk is on validation of pre-silicon models: from the point of view of function as well as target cycle-per-instruction (CPI) performance. We review some of the new approaches in industry and academia in attempting to take an integrated view of automation in this area. We report our own experiences based on recent PowerPC processor development projects.

Speaker Bio

Pradip Bose received his B. Tech. degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, India in 1977 and the M.S. and Ph.D degrees in Electrical and Computer Engineering from the University of Illinois, Urbana-Champaign, in 1981 and 1983 respectively. Since May 1983, Dr. Bose has been a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. During 1992-94, Dr. Bose was on assignment at IBM Austin, where he served as the lead performance engineer during the definition and evaluation of a processor, which eventually evolved into IBM's POWER3 microprocessor. During the 1989-90 academic year, Dr. Bose was a Visiting Associate Professor at Indian Statistical Institute, Calcutta, India as part of a sabbatical leave assignment from IBM. During that year, he worked on the application of artificial intelligence techniques to problems in VLSI CAD. His current research interests include: high performance computer architectures and their performance evaluation, verification and testing.