At CMU my research has been in compilers and reconfigurable computing.
Here are brief summaries and links to some of my projects:

Reconfigurable Computing

CPU+RFU
This project involves the implementation of a hybrid processor that comprises a general purpose CPU and reconfigurable function unit (RFU). The hybird processor takes programs that are partitioned into code+configurations and executes them. Various issues are considered - concurrent execution of the CPU and RFU, memory accesses by both CPU and RFU, speculative execution and squashing of the RFU, being some considerations. I am also implementing a compiler pass to extract hyperblocks in code to be executed profitably on the RFU.

Configuration Caching and Swapping
Implemented a new configuration caching algorithm for maintaining configurations on the FPGA during program execution. The new algorithm performs significantly better than existing ones. Also studied the performance of multi-level caching. Check the Publicationssection for the paper on this subject.

Power-Aware Computing

Compiler-directed Performance Enhancement for Partitioned Memory/Cache Systems
A novel technique was developed, involving compiler and hardware support, to enhance the performance of systems with power-partitioned cache and memories. Such systems exhibit significant power-reductions, but also suffer in performance. Our strategy successfully brings performance closer to conventional systems while maintain the benefits of power reduction by partitioned caches and memory. A compiler pass, and augmented simulation suite were developed.

VLSI-CAD
Recursive Min-Cut Placer
A VLSI placement tool. Has a parameterized design, with some advanced features like 4-way partitioning and clustering. Details at the project website.

Transistor Level Equivalence Checking
A simple tool to evaluate differences between transistor- and gate-level netlists using BDDs. The project website is here.

@IBM
Test-Nano Kernel
At IBM Austin I worked with the POWER4 development group on the Processor Verification and Test Tool Development team. I was involved with I/O stress testing and verification of IBM's POWER4 microprocessor. This involved implementing benchmarks within a MINIX-like microkernel that executes on the processor and generates stress testing information.

Undergraduate
Reconfigurable Architecture Kit
My undergraduate thesis project. Implemented a parameterized collection of modules for implementing RISC-like processor cores on Xilinx XC4000 FPGAs. The generic core implements a configurable ISA, pipeline and buswidth. Heres my thesis .

Simulator for IBM SP/2 Multiprocessor
Summer internship at IISc Bangalore during May-July 1998. I was a member of a group of ~10 students involved in developing a simulator for the IBM RS6000 SP/2 multiprocessor system.