FIRST INTERNATIONAL WORKSHOP ON PARALLEL PROCESSING The Oberoi, Bangalore, India December 26-31, 1994 ADVANCE PROGRAMME With support from Department of Science and Technology, Government of India Center for Development of Advanced Computing (CDAC) Board of Research in Nuclear Sciences, India Digital Equipment (India) Limited Tata Information Systems Limited (TISL) Center for Development of Telematics (C-DOT) National Aerospace Laboratories (NAL) Infosys Technologies Limited Motorola India Electronics Private Limited IEEE Bangalore Chapter In co-operation with IEEE Computer Society Technical Committee on Parallel Processing (TCPP) IEEE Computer Society Technical Committee on Computer Architecture (TCCA) ORGANIZING COMMITTEE WORKSHOP CO-CHAIRS Viktor K. Prasanna, USC Vijay P. Bhatkar, CDAC Internet: prasanna@halcyon.usc.edu Vox: 91-212-331 507 PROGRAM CO-CHAIRS Lalit Patnaik, Indian Institute of Science Satish Tripathi, Univ. of Maryland PROGRAM COMMITTEE Arvind, MIT Sridhar Mitta, Wipro Infotech Ltd. P. C. P. Bhatt, IIT, Delhi C. R. Muthukrishnan, IIT, Madras S. Biswas, IIT, Bombay David Nassimi, NJIT Mary M. Eshaghian, NJIT M.V. Pitke, TIFR Richard F. Freund, NRaD Sartaj Sahni, Univ. of Florida Anoop Gupta, Stanford Univ. R. K. Sen, IIT, Kharagpur Kai Hwang, USC Y. Singh, Tata Info. Systems Ltd. Sitharama Iyengar, LSU Vaidy Sunderam, Emory Univ. Lawrence Jenkins, IISc. K. S. Yajnik, Center for Mathematical H. K. Kaura, BARC Modeling and Computer Simulation PROGRAM CO-ORDINATOR Ajay Gupta, Western Michigan University PROCEEDINGS CO-CHAIRS Ramesh Rao, Univ. of California, San Diego C. P. Ravikumar, IIT, Delhi FINANCE CO-CHAIRS Suresh Chalasani, Univ. of Wisconsin A. K. P. Nambiar, CDAC COMMERCIAL EXHIBITS/VENDOR PRESENTATIONS CO-CHAIRS G. H. Visweswara S. Sasi Kumar CAD Group, MC Division CDAC ITI, Dooravaninagar Ramanashree Plaza, 2/1 Brunton Road Bangalore - 560 016, India Bangalore - 560 025, India Vox: 91-80-851 1211 Extn. 3628 Vox: 91-80-558 4271 Fax: 91-80-851 0971/851 1724 Fax: 91-80-558 4893 Internet: vish@itibang.ernet.in Internet: sasi@cdacb.ernet.in LOCAL ARRANGEMENTS CHAIR Anirban Basu, CDAC, Bangalore Vox: 91-80-558 4982 Fax: 91-80-558 4893 PUBLICITY CO-ORDINATORS Dhabaleswar K. Panda Anil Rao C. P. Ravikumar The Ohio State University Universitiet Utrecht IIT, Delhi IWPP '94 - OVERVIEW Monday, December 26 (page 4) 08:00 AM - 06:00 PM Registration 09:00 AM - 01:00 PM Tutorial 1 02:00 PM - 06:00 PM Tutorial 2 Tuesday, December 27 (pages 5 - 8) 08:00 AM - 06:00 PM Registration 08:15 AM - 09:00 AM Opening Remarks Inaugural Address 09:00 AM - 10:00 AM Keynote Address 1 10:00 AM - 10:30 AM Morning Break 10:30 AM - 12:30 PM Session 1 10:30 AM - 06:00 PM Commercial Exhibits 12:30 PM - 01:30 PM Lunch 01:30 PM - 03:30 PM Session 2 03:30 PM - 04:00 PM Afternoon Break 04:00 PM - 06:00 PM Session 3 06:00 PM - 08:00 PM Dinner 08:00 PM - 10:00 PM Session 4 Wednesday, December 28 (pages 9 - 12) 08:00 AM - 06:00 PM Registration 08:30 AM - 09:30 AM Keynote Address 2 09:30 AM - 10:00 AM Morning Break 10:00 AM - 12 Noon Session 5 10:00 AM - 06:00 PM Commercial Exhibits 12 Noon - 01:30 PM Lunch 01:30 PM - 03:30 PM Session 6 03:30 PM - 04:00 PM Afternoon Break 04:00 PM - 06:15 PM Session 7 06:15 PM - 08:00 PM Dinner 08:00 PM - 10:00 PM Session 8 Thursday, December 29 (pages 13 - 16) 08:00 AM - 06:00 PM Registration 08:30 AM - 09:30 AM Keynote Address 3 09:30 AM - 10:00 AM Morning Break 10:00 AM - 12 Noon Session 9 10:00 AM - 06:00 PM Commercial Exhibits 12 Noon - 01:30 PM Lunch 01:30 PM - 03:30 PM Session 10 03:30 PM - 04:00 PM Afternoon Break 04:00 PM - 06:00 PM Session 11 06:00 PM - 08:00 PM Dinner 08:00 PM - 10:00 PM Session 12 Friday, December 30 (pages 17 - 19) 08:00 AM - 06:00 PM Registration 08:30 AM - 09:30 AM Keynote Address 4 09:30 AM - 10:00 AM Morning Break 10:00 AM - 12 Noon Session 13 10:00 AM - 12 Noon Industrial Track 1 12 Noon - 01:30 PM Lunch 01:30 PM - 03:30 PM Session 14 01:30 PM - 03:30 PM Industrial Track 2 03:30 PM - 04:00 PM Afternoon Break 04:00 PM - 06:00 PM Session 15 04:00 PM - 06:00 PM Industrial Track 3 Saturday, December 31 (page 20) 08:00 AM - 12 Noon Registration 09:00 AM - 01:00 PM Tutorial 3 02:00 PM - 06:00 PM Tutorial 4 06:00 PM - Workshop Adjourns MONDAY, DECEMBER 26 9:00 AM - 1:00 PM Tutorial 1 Data Parallel Programming using High Performance Fortran Piyush Mehrotra Institute for Computer Applications in Science and Engineering Description: High Performance Fortran is a set of extensions to Fortran 90 designed to facilitate data parallel programming on a wide variety of parallel architectures. These extensions provide the user with high level mechanisms to control the distribution of data and work across the target architecture, while leaving the low level machine specific details such as, data communication, to the underlying compiler/runtime system. This tutorial will use a sequence of examples drawn from scientific applications to highlight important features of the language. Lecturer: Piyush Mehrotra received his Ph.D. in Computer Science from the University of Virginia. He was a staff scientist at ICASE for two years before joining the faculty of the Department of Computer Science, Purdue University. He spent four and a half years at Purdue before returning to ICASE as a Senior Staff Scientist where he is currently leading the System Software Research effort. His main research interests are programming environments, compilers, and runtime systems for parallel and distributed environments. Among other activities, he has been a member of the High Performance Fortran Forum since its inception and has been intimately involved with the design of the language. 2:00 PM - 6:00 PM Tutorial 2 Introduction to Message Passing and Programming with PVM D. N. Jayasimha The Ohio State University Description: PVM (Parallel Virtual Machine) is a portable message passing library which runs on a variety of computing platforms from a cluster of workstations to masssvely parallel processors. The first part of the tutorial will be a brief introduction to parallel architectures and programming. The main part will detail the use of PVM to write parallel programs. The last part will discuss guidelines for writing efficient parallel programs and include a demonstration. Knowledge of C or FORTRAN and programming experience is assumed. The intended audience include scientists and engineers who wish to parallelize their applications. Lecturer: D. N. Jayasimha received his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. He is on the faculty in Computer and Information Science at the Ohio State University. He was a Visiting Research Scientist at the NASA Lewis Research Center during 1993-94 where he worked on parallelizing applications using PVM and other message passing libraries. His research interests are in the areas of communication and synchronization in parallel computation, parallel architectures, and parallel applications. TUESDAY, DECEMBER 27 8:15 AM - 9:00 AM Opening Remarks: Viktor Prasanna, Vijay Bhatkar, Lalit Patnaik, Satish Tripathi. Inaugural Address: N. Vittal, Secretary, Department of Electronics, Government of India. 9:00 AM - 10:00 AM Keynote Address 1: Future of Parallel Programming, Arvind, MIT 10:00 AM - 10:30 AM Morning Break 10:30 AM - 12:30 PM Session 1: Architecture I Chair: David Kahaner, ONR-Asia. Issues in Designing Scalable Systems with k-ary n-cube Cluster-c Organization, Dhabaleswar K. Panda and Debashis Basak, Ohio State University. A Performance Model for Virtual Channel Flow Control in Hypercubes, Younes M. Boura and Chita R. Das, Pennsylvania State University. Dynamic Stream Selection on Multiple Instruction Stream Superscalar Architectures, Miquel Nicolau i Vila and Teodor Jove I Lagunas, Universitat Ramon Llull. The Impact of Coarse Grain Parallelism: A Study of Proteus and Paragon Supercomputers, Allen M. Sansano, Hsiao-Ping Tseng and Arun K. Somani, University of Washington. Fault-Tolerant Hierarchical Network of Hypercubes, M. Kumar, Curtin University of Technology, Australia. Computing with Faulty SIMD Hypercubes, C. S. Raghavendra, Washington State University. A New Family of Low Diameter Network Topologies with Multiple Loops, Srabani Sen Gupta, Rajib K. Das, Krishnendu Mukhopadhyaya and Bhabani P. Sinha, Indian Statistical Institute, Calcutta. MPP - The Next Generation: Massively Parallel I/O, Frank J. Rinaldo, Fermi National Accelerator Laboratory. 10:30 AM - 6:00 PM Commercial Exhibits (TBA) 12:30 PM - 1:30 PM Lunch Break 1:30 PM - 3:30 PM Session 2: Algorithms I Chair: Heonchul Park, Samsung Electronics Ltd., Korea. Performing Dynamic Permutations on a Coarse Grain Parallel Machine, Ravi Shankar and Sanjay Ranka, Syracuse University. A Parallel Search & Learn Algorithm for Graph Coloring, C. P. Ravikumar and Rajat Aggarwal, Indian Institute of Technology, Delhi. Scalable Parallel Formulations for Sparse Matrix Factorization and Interior Point Methods, Anshul Gupta, Vipin Kumar and George Karypis, University of Minnesota. Mutual Exclusion Based Approach for Adaptive Load Sharing in Homogeneous Distributed Systems, P. Subramanyam, C. R. Muthukrishnan and R. Satyanarayanan, Indian Institute of Technology, Madras. A New Shift Switch Model and Large-Size Parallel Counters, Rong Lin, State University of New York, Geneseo. Progressive Generation of Parallel Solutions for Formally Specified Problems, Mathieu Buffo, Erik Urland, Jose Rolim and Didier Buchs, Centre Universitaire du Informatique-Universite de Geneve. Parallel Discrete-Event Simulation: Algorithms and Analysis, Sajal K. Das and Falguni Sarkar, University of North Texas. A Fast Parallel Thinning Algorithm, Weian Deng, S. Sitharama Iyengar and Nathan E. Brener, Louisiana State University. 3:30 PM - 4:00 PM Afternoon Break 4:00 PM - 6:00 PM Session 3: Software I Chair: Shrikant Inamdar, Motorola India Electronics Limited. Digital's HPF/Fortran 90 Compiler: Meeting the Challenge of Generating Efficient Code on a Workstation Farm, Ranga Raj, Digital Equipment (India) Limited. Application-Driven Development of an Integrated Tool Environment for Distributed Memory Parallel Processors, C. Clemen, K. M. Decker, A. Endo, J. Fritscher, G. Jost, N. Masuda, A. Muller, W. Sawyer, E. de Sturler and B. J. N. Wylie, Swiss Scientific Computing Center CSCS. Compiling Fortran-D for Multiprocessors, Ananda R., Gautam S. and Sanjeev Aggarwal, Indian Institute of Technology, Kanpur. STraNPP: Source to Source Translator for Network-Based Parallel Processing, Alfred C. K. Heng, Wentong Cai, Francis B. S. Lee and K. K. Lee, Nanyang Technological University, Singapore. EC: A Language for Distributed Computing, Ashok Kumar Naik and Gautam Barua, Indian Institute of Technology, Kanpur. Interaction Paradigms for Distributed Object-Oriented Programming, T. S. Mohan, Indian Institute of Science. Efficient Implementation of High Performance Fortran via Adaptive Scheduling, L.V. Kale and Ed Kornkven, University of Illinois, Urbana-Champaign. An Overview of the Opus Language and Runtime System, Piyush Mehrotra and Matthew Haines, NASA Langley Research Center. 6:00 PM - 8:00 PM Dinner Break 8:00 PM - 10:00 PM Session 4: Applications I Chair: Sajal K. Das, University of North Texas. Parallel Implementation of A Robust Algorithm for Tracking Moving Objects, S. Das, Indian Institute of Technology, Madras and B. N. Chatterjee, Indian Institute of Technology, Kharagpur. Parallel Implementation of the EM Algorithm for PET Image Reconstruction, K. Rajan, L. M. Patnaik and J. Ramakrishna, Indian Institute of Science. High Performance Multi-standard Image Compression Coprocessor for Multi-media, Heonchul Park, Samsung Electronics. A VLSI Architecture for Approximate Tree Matching, Raghu Sastry and N. Ranganathan, University of South Florida. Parallel Image Processing Software on ANUPAM, Rashmi Rastogi, Sudhir Shetiya, Laxmi Phadke and Sunanda Shouche, Bhabha Atomic Research Centre, Bombay. Interactive Parallel Code Generator for Flosolver Parallel Computer, C. R. Srinivasan, National Aerospace Laboratories, Bangalore. Application of JPEG Algorithm on SHIVA Parallel Architecture, Savitridevi G. Bevinakoppa, Nalin K. Sharda and Hema Sharda, Victoria University of Technology. Recoverable Data Structures for Supporting Parallel Database Applications, Krithi Ramamritham and Lory Molesky, University of Massachusetts. 10:00 PM Adjourn for the day WEDNESDAY, DECEMBER 28 8:30 AM - 9:30 AM Keynote Address 2: SmartNet Scheduling for Heterogeneous Computing Richard F. Freund, Naval Research and Development Center 9:30 AM - 10:00 AM Morning Break 10:00 AM - 12:00 Noon Session 5: Architecture II Chair: S. V. Raghavan, Indian Institute of Technology, Madras. Parallel Computations on Heterogeneous Workstation Clusters and Distributed-Memory Parallel Computers, Vikram A. Saletore and J. Jacob, Oregon State University. RENNS- an Experimental Computer System with a Reconfigurable Interconnection Network, Jon G. Soldheim and Gaute Myklebust, Norwegian Institute of Technology. Comparison of Multiplexing Schemes for Wormhole-Routed Distributed Memory Multiprocessors, Kant C. Patel, Jeff A. May and D. N. Jayasimha, Ohio State University. An Integrated Approach to Distributed Shared Memory, Alan L. Cox, Sandhya Dwarkadas and Willy Zwaenepoel, Rice University. Twine RISC: A High Performance Multithreaded RISC Architecture, Rajat Moona, Massachusetts Institute of Technology. Reliability Evaluation of Multistage Interconnection Networks by Network Decomposition, C. R. Tripathy, R. N. Mahapatra, R. B. Mishra and S. Patra, Indian Institute of Technology, Kharagpur. Cumulative Performance Measures for Gracefully Degradable Multistage Interconnection Networks, Amiya Bhattacharya, Ramesh Rao and Ting-Ting Y. Lin, University of California-San Diego. An Incessantly Coherent Cache Scheme for Shared Memory Multithread Systems, S. K. Nandy and Ranjani Narayan, Massachusetts Institute of Technology. 10:00 AM - 6:00 PM Commercial Exhibits (TBA) 12:00 Noon - 1:30 PM Lunch Break 1:30 PM - 3:30 PM Session 6: Algorithms II Chair: Rong Lin, State University of New York at Geneseo. Task Redistribution in Faulty Networks Using Evolutionary Strategies, Garry Greenwood, Ajay Gupta and Mark Terwilliger, Western Michigan University. Shared Memory Multiprocessor Implementation of Volume Rendering, S. Manohar and C. E. Prakash, Indian Institute of Science. Superlinear Speedup in Multiprocessing Environment, Vishwani D. Agrawal, AT&T Bell Labs. An Efficient Algorithm for the Partitionable Independent Task scheduling Problem using Lookahead - Search, R. S. Ramesh and C. Shiva Rama Murthy, Indian Institute of Technology, Madras. Algorithms for Efficiently Partitioning a Class of Parallel Computations, Bhagirath Narahari and Rahul Sinha, George Washington University. On Computing Kirkpatrick Decomposition in Parallel, Sanjeev Saxena, Indian Institute of Technology, Kanpur. A Parallel Evolutionary Programming Based Channel Router, B. B. Prahlada Rao and R. C. Hansdah, Indian Institute of Science. Analysis and Modeling of Image Processing Algorithms on Parallel Computing Systems, N. Comino and V. Lakshmi Narasimhan, University of Queensland. 3:30 PM - 4:00 PM Afternoon Break 4:00 PM - 6:15 PM Session 7: Software II Chair: Y. Singh, Tata Information Systems Limited. ANUPAM Programming Environment, S. M. Mahajan, P. S. Dhekne, H. K. Kaura, K. Ramesh and K. Rajesh, Bhabha Atomic Research Centre, Bombay. A Loop Distribution Technique for Parallel Machines for Irregular Computations, Mohammed Raziuddin, Ravi Ponnusamy and Alok Choudhary, Syracuse University. A Framework for Multithreaded X Client Development, Murali V. Srinivasan, SunSoft Inc. Performance of ScaLapack on PARAM, Kamal Kumar Jain, M. Kishore Kumar and Anirban Basu, Centre for Development of Advanced Computing, Bangalore. A Comparative Study of Design Approaches for Parallel Programming Languages, Wolfgang Gellerich and M. M. Gutzmann, University of Stuttgart. A Model for Parallel Processing Software Development, Rajib Mall, Indian Institute of Technology, Kharagpur. The PARADIGM Compiler for Distributed Memory Message Passing MIMD Multicomputer, P. Banerjee, J. Holm, A. Lain, D. Palermo, S. Ramaswamy and E. Su, University of Illinois, Urbana-Champaign. High Performance Fortran Type Compilers for Irregular and Block Structured Problems, Joel Saltz, Raja Das, Yuan-Shin Hwang, Bongki Moon and Shamik Sharma, University of Maryland-College Park. Distributing Code in A Parallel Fine Grain Machine, Youssef Latrous and Guy Mazare, LGI/IMAG, France. 6:15 PM - 8:00 PM Dinner Break 8:00 PM - 10:00 PM Session 8: Applications II Chair: Bhagirath Narahari, George Washington University. Integration of Task and Data Parallelism, R. Krishnaiyer and B. Avalani, Syracuse University. A Parallel Discrete Event Simulator and its Application to Circuit Simulation, Rajive Bagrodia, University of California at Los Angeles. Stability and Performance of Distributed Simulators for Open Queueing Networks, Rajeev Shorey and Anurag Kumar, Indian Institute of Science. Application of Timed Token Protocol for Communications in an Application Specific Parallel Processing Architecture for Real Time Control of an MTDC System, V. Shyam and H.S. Chandrasekharaiah, Indian Institute of Science. Porting Realistic Applications to HPF - a Case Study, Sumana S. and U. Nagaraj Shenoy, Centre for Development of Advanced Computing, Bangalore. High Performance Computer for Land Cover Dynamics, Larry Davis, Rama Chellappa, Joel Saltz, Joseph J'aJ'a, Rahul Parulekar and Alan Sussman, University of Maryland-College Park. Large Parallel Compact Coding of Satellite Images with Wavelet Packet, Andreas Uhl, University of Slazburg-Austria. Distributed Quad-Tree Processing of Vector Data, S. Venkatesh and D. Kieronska, Curtin University of Technology, Australia. 10:00 PM Adjourn for the day THURSDAY, DECEMBER 29 8:30 AM - 9:30 AM Keynote Address 3: Compiler & Library Support for Irregular Problems on High Performance Architectures Joel Saltz, University of Maryland 9:30 AM - 10:00 AM Morning Break 10:00 AM - 12:00 Noon Session 9: Architecture III Chair: J. Mohan Kumar, Curtin University of Technology, Australia. Issues in Understanding the Scalability of Parallel Systems, Umakishore Ramachandran, H. Venkateswaran, Anand Sivasubramaniam and Aman Singla, Georgia Institute of Technology. Parallel Detection of Multiple Faults in Redundant Path Multistage Interconnection Network, U. Maulik, Visva Bharathi University, Shantiniketan, S. Bandyopadhyay, Indian Statistical Institute, Calcutta and S. Bhattacharya, Technical Teachers' Training Institute, Calcutta. A K-level Binary Tree Embedded in a Symmetrical Reconfigurable Network, Tirumale Ramesh, Saginaw Valley State University. A Cost Effective Unidirectional Binary (UB)- Tree Architecture, Ravi Mittal and Ashok K. Agrawala, University of Maryland-College Park. Design of a High Speed Communication Controller for a Multicomputer System - An FSM approach, M. Srinivasan, B. Nagabhushana and M. Muralidharen, Indian Institute of Science. Memory Coupled Scalable Multiprocessors, A. Varshneya, B. Madan and M. Balakrishnan, Indian Institute of Technology, Delhi. Fault Tolerance in Hypercube Based Parallel Architectures, N. Singhi and S. Sanyal, Tata Institute of Fundamental Research, Bombay and I. Shriniwas, Victoria Jubilee Technical Institute, Bombay. Data Communication in the Star Communication Network, Dilip K. Saikia and Ranjan K. Sen, Indian Institute of Technology, Kharagpur. 10:00 AM - 6:00 PM Commercial Exhibits (TBA) 12:00 Noon - 1:30 PM Lunch Break 1:30 PM - 3:30 PM Session 10: Software III Chair: N. Balakrishnan, Indian Institute of Science. Partitioning Problems in Heterogeneous Distributed Computing, M. Ashraf Iqbal, Engineering University-Pakistan. Transformation Based Development of Efficient Programs for Massively Parallel Architectures, M. M. Gutzmann, University of Jena and S. Kinderman, University of Erlangen. Runtime Support for Task-Parallel Languages, I. Foster, C. Kesselman and S. Tuecke, California Institute of Technology. Optimal Scheduling Algorithm for Distributed Memory Machines, Sekhar Darbha and Dharma P. Agrawal, North Carolina State University. An Efficient Algorithm for Partitioning of Parallel Programs for Near-Optimal Scheduling, Huade Li, Piyush Maheshwari and Hong Shen, Griffith University. The Effect of Inter-process Communication on Scheduling in Multiprogrammed Distributed Memory Systems, Shikharesh Majumdar and Yiu Ming Leung, Carleton University. Design of an Application Development Toolkit for HPF/Fortran 90D, Manish Parashar, Salim Hariri, Tomasz Haupt and Geoffrey C. Fox, Syracuse University. GAPPE: Graphical Animation of Parallel Program Execution Alfred C. K. Heng, Wentong Cai and Shu Fei Chia, Nanyang Technological University, Singapore. 3:30 PM - 4:00 PM Afternoon Break 4:00 PM - 6:00 PM Session 11: Software IV Chair: Ajay Gupta, Western Michigan University Compiling Irregular Programs for Distributed Memory Architectures, Raja Das and Joel Saltz, University of Maryland-College Park. Advanced Parallel Usage Analysis, M. Manjunathaiah and D. Nicole, University of Southampton. PRETSEL - A Parallel Real Time Specification Language for Real Time Systems on Parallel Computers, Melissa Benincasa, Alok N. Choudhary, Vijay Gehlot, Richard Metzger and Bhagirath Narahari, Syracuse University. Techniques for Compiling and Executing HOF Programs on Shared Memory and Distributed Memory Parallel Systems, Larry Meadows, Vince Schuster, Zeki Bozkus, Doug Miles and Mark Young, The Portland Group, Inc. A Restructuring Compilation Method for the Xputer Paradigm, K. Schmidt and R. W. Hartenstein, University of Kaiserslautern-Germany. Declarative Programming on PARAM, Manish Gupta and Vijay Chandru, Indian Institute of Science. Parallelization of Loops with Affine Dependencies, Patrick M. Lenders, University of New England-Australia. Toward Scalable Parallel Software: Interfacing to non-von Neumann Programming Environments, George K. Thiruvathukal and Thomas W. Christopher, R. R. Donelley and Sons, Co. 6:00 PM - 8:00 PM Dinner Break 8:00 PM - 10:00 PM Session 12: Applications III Chair: M. Ashraf Iqbal, Engineering University-Pakistan. An Interleaved Systolic Adaptive Architecture for Video Ghost Elimination, J. Thomas and S. Balakrishnan, Indian Institute of Science. Performance Analysis of Task Farming Programs in Heterogeneous Multi-User Environments, Thomas Schnekenburger, Technische Universitaet Muenchen. Parallel I/O Access of Multiversion Data Structures, Peter J. Varman, Rice University and Nanyang Technical University, Singapore and Rakesh M. Verma, University of Houston. Multi-Installment Load Distribution Strategy in Networks with Communication Delays, V. Bhardwaj, D. Ghose and V. Mani, Indian Institute of Science. Parallelization of Multiblock Euler code AMES, Lakshmi Soundararajan, K. Murali Krishna and K. P. Singh, Aeronautical Development Agency. Experimental Studies of Fine Grain Reconfigurable Architectures, R. S. Bajwa, R. Kasamsetty, R. M. Owens and M. J. Irwin, Pennsylvania State University. A Platform to Study Dynamic Load Balancing Functions for Parallel Logic Systems, J. Briat, S. E. Kannat, J. P. Kitajima and E. Morel, LGI-IMAG-INPG-France. Exploiting Neural Network Parallelism, Suthiksn Kumar, David Wo, M. Palaniswami and Kevin Forward, University of Melbourne-Australia. 10:00 PM Adjourn for the day FRIDAY, DECEMBER 30 8:30 AM - 9:30 AM Keynote Address 4: System Architectures for High Performance Computing in the 1990s, Tilak Agerwala, IBM 9:30 AM - 10:00 AM Morning Break 10:00 AM - 12:00 Noon Session 13: Architecture IV Chair: R. Srinivasan, National Aerospace Laboratories. Petersen-Twisted Cube: A New Multiprocessor Interconnection Network, M. P. Sebastian, Lawrence Jenkins and P. S. Nagendra Rao, Indian Institute of Science. Transputer-based Embedded Parallel Processing in Ground Systems for Satellite Telemetry, Tushar K. Hazra and Bhavana Singh, Martin Marietta Services, Inc. A New Issue Method to Conserve Instruction Bandwidth, Vinod G. Kulkarni and M. R. Bhujade, Indian Institute of Technology, Bombay. EQUALS - The Next Generation, Owen Kaser, University of New Brunswick, C. R. Ramakrishnan, SUNY Stony Brook and R. C. Sekar, Bellcore. Performance Comparison of Various Latency Tolerant Architectures, Swaminathan Ramany, University of Saskatchewan, Canada and K. Gopinath, Indian Institute of Science. Synthesis of Energy Efficient Configurable Processor Arrays, V. Viswanathan and S. Ramanathan, Indian Institute of Science. Scalable Expanders from Finite Geometries, Rama K. Govindaraju and Mukkai S. Krishnamoorthy, Rensselaer Polytechnic Institute. Using DPUs Interrupting Messages in Network Computing, David M. Arnow, Brooklyn College. 10:00 AM - 12:00 Noon Industrial Track 1 (TBA) 12:00 Noon - 1:30 PM Lunch Break 1:30 PM - 3:30 PM Session 14: Algorithms III Chair: Ramesh Rao, University of California, San Diego. Efficient Parallel R-tree Algorithm, Dipak Pravin Doctor and Hal Sudborough, University of Texas at Dallas. Synchronization-Based Parallelization, A. Jayawardena and Patrick Lenders, University of New England-Australia. A Parallel Algorithm for the Calculation of Kronecker Products, etc. R. J. White and N. Sharda, Victoria University of Technology-Australia and C. Osborne, Monash University, Clayton, Australia. A Parallel Random Search Global Optimization Techniques, K. Deep, Central Building Research Institute, Roorkee and D. J. Evans, Loughborough University of Technology. Primitives for Problems using Hierarchical Algorithms on Distributed Memory Machines, Sanjay Goil, Syracuse University. Developing Self-Stabilizing Coloring Algorithms via Systematic Randomization, Sandeep K. Shukla, Daniel J. Rosenkrantz and S. S. Ravi, State University of New York, Albany. Parallel Construction of the Suffix Array, C. H. Lee and I. W. Chan, National University of Singapore. Performance Measurements of Parallel Algorithms for Linear Programming Problems, Alfred Loo, Lingnan College-Hong Kong. 1:30 PM - 3:30 PM Industrial Track 2 (TBA) 3:30 PM - 4:00 PM Afternoon Break 4:00 PM - 6:00 PM Session 15: Applications IV Chair: Ian Foster, Argonne National Laboratories. Parallel Implementation of the Three Dimensional Turbulent Viscous Flow Code VASBI, Biju Uthup, Aeronautical Development Agency, Bangalore, K. Rajesh, Bhabha Atomic Research Center, Bombay and S. M. Deshpande, Indian Institute of Science. An Experimental Study of the Effects of Heterogeneity and Data Partitioning on the Performance of Parallel Applications, Anantha K. Bangalore and Daniel A. Menasce, George Mason University. The Matvec Library for Data Parallel Computing and its Applications in Parallelization of CFD Algorithms, G. M. Shroff, Indian Institute of Technology, New Delhi, A. Mukhopadhyay, S. H. Rao and R. K. Mansharamani, Tata Research Development and Design Centre, Pune. Implementation and Performance Evaluation of Massively Parallel Algorithms for Block Updating Least Squares, Erricos J. Kontoghiorghes and Elias Dinenis, City University, London. The Porting of Parallel Applications from Transputer Based Machines to the Intel Paragon Supercomputer, W. J. Cosshall, Swinburne University of Technology and I. Morrison, University of Melbourne. Hierarchical Censored Production Rules: Some Avenues for Parallelization, Renu Varshneya and K. K. Bharadwaj, Jawaharlal Nehru University, New Delhi. A Step Towards User Independent Image Processing Operating Environment for Distributed Processing, Haresh S. Bhatt and C. V. S. Prakash, Space Applications Center, Ahmedabad and A. K. Aggarwal, Gujarat University, Ahemdabad. Protocol Support for Application in VISTAnet Gigabit Network, Raj K. Singh, Stephen G. Tell and Shaun J. Bharrat, University of North Carolina. 4:00 PM - 6:00 PM Industrial Track 3 (TBA) 6:00 PM : Contributed Sessions End SATURDAY, DECEMBER 31 9:00 AM - 1:00 PM Tutorial 3 Parallel Programming in Fortran M Ian Foster Argonne National Laboratories Description: Fortran M --- M for Modular --- is a small extension of Fortran 77 for task-parallel programming. Fortran M has object-oriented features and provides compile-time guarantees of deterministic execution. Compilers are available for many parallel and networked computers. The tutorial will provide an introduction to programming in Fortran M, focusing on the requirements of scientific and engineering applications. Lecturer: Ian Foster received his Ph.D. from Imperial College in Computer Science in 1988. In 1989, the Strand programming system that he designed was awarded the British Computer Society's award for technical innovation. He is currently a Scientist in the Mathematics and Computer Science Division of Argonne National Laboratory. His latest book, "Designing and Building Parallel Programs," is being published simultaneously by Addison-Wesley and on the World Wide Web. 2:00 PM - 6:00 PM Tutorial 4 Scalability of Parallel Systems H. Venkateswaran Georgia Institute of Technology Description: A parallel system is an application-architecture combination. Scalability is a term that is often used to signify the "goodness" of parallel systems. A good understanding of this notion may be used to: select the best architecture platform for an application domain, predict the performance of an application on a larger configuration of an existing architecture, and glean insight on the interaction between an application and an architecture to understand the scalability of other application-architecture pairs. In this tutorial, we present a survey of metrics used to capture this notion; the merits and demerits of these metrics; the factors that lead to overheads in a parallel system; the techniques such as experimentation, simulation, and analytical modeling used in scalability studies; and recent advances in understanding the scalability of parallel systems. Lecturer: H. Venkateswaran received his Ph.D. from the University of Washington, Seattle in 1986. He is currently an Associate Professor in the College of Computing at Georgia Institute of Technology, Atlanta. His primary research interests are in computational complexity theory and parallel computation. His research interests in parallel computation concerns both theoretical and practical issues. He is a co-principal investigator in a project that studies the impact of architectural features on the performance of parallel algorithms. LOCATION About Bangalore: The venue for the First International Workshop on Parallel Processing is the city of Bangalore. Bangalore is the capital of the state of Karnataka and is the fifth largest city in India. It is about 250 Kms from Madras and is about 800 Kms from Bombay. Situated at an altitude of approximately 1000 Meters above sea level, Bangalore has a population of over three million people. The city is the home to the Indian Institute of Science, many aerospace and high technology industries including the Center for Development of Advanced Computing and is often called the Silicon valley of India. The city's prominent buildings include the Vidhana Soudha which is the Legislative building and the palace of the maharaja of Mysore. From Bangalore many nearby historic and archeological sites can be easily reached. Visa and Passport: All participants who are not citizens of India must obtain a valid visa from Indian Consulates or High Commissions. The procedure may take some time, consult with your travel agent in advance. Currency: The currency is the Indian Rupee. The conversion rate at the time of this publication is 1 US $ to Rs. 31.50. Credit cards are accepted in most luxury hotels but not in most commercial establishments. The Reserve Bank of India may have certain restrictions on converting Rupees to other currencies. For details, check with an Indian Consulate or your travel consultant. Time and Weather: The Indian Standard Time(IST) is 5 1/2 hours ahead of the Greenwich Mean Time(GMT) and is 13 1/2 hours ahead of the U. S. Pacific Standard Time(PST). In December/January the climate is mildly tropical with temperatures averaging about 22 degrees Celsius (approx. 70 degrees Fahrenheit) during the day and it is about 14 degrees Celsius (approx. 55 degrees Fahrenheit) during the night. Travel: Many international carriers fly to India. Since Bangalore does not have an international airport one has to fly into Bombay, New Delhi or Madras and connect to Bangalore. Indian Airlines and several private private airlines connect Bangalore with major cities on a daily basis. It is advisable to make reservations early as travel is heavy during the months of December and January. The workshop does not endorse any travel agency, however, to assist international travellers with late reservations a block of seats has been reserved. You may contact Globalink Travels in the Los Angeles area at 818-907-8302 (FAX) and 818-972-9525 (VOX) for details. Accommodation: The Oberoi is offering a special rate of US $ 129.50 (per night, single or double) for workshop participants. The rate includes all taxes. The Oberoi is a deluxe hotel situated on Mahatma Gandhi road, which is the city's most famous promenade. The hotel has a 24 hour business center which has a comprehensive range of facilities, including offices for private use and a board room for select meetings. The airport is less than 10Kms from the hotel. The cost of the ride to or from the airport can vary, and a one-way taxi ride will cost around US $6 including tip. Additional information about Bangalore(as well as places of interest in the state of Karnataka and in India) can be found on the World Wide Web (WWW) under: http://spiderman.bu.edu/misc/karnataka/tourism/index.html http://spiderman.bu.edu/misc/karnataka/cities/bangalore/index.html http://spiderman.bu.edu/misc/karnataka/index.html http://enuxsa.eas.asu.edu/~sridhar/places/india.html ADVANCE REGISTRATION FORM IWPP '94 December 26-31, 1994 The Oberoi, Bangalore, India Please Print: Name: ________________________________________________________________ Company/University: __________________________________________________ Address/Mail Stop: ___________________________________________________ City/State/Zip/Country: ______________________________________________ Daytime Number: ____________________ Fax Number: _____________________ IEEE Membership Number: ______________ E-Mail: _______________________ Dietary needs: Vegetarian _________________ Spicy ________________ Please Circle Appropriate Fees: ... Workshop Registration Fees: IEEE Member Non-Member Student Advance Registration (Until Nov.25) US $80 US $100 US $80 Late/Onsite Registration (After Nov.26) US $100 US $125 US $100 The registration fee includes a copy of the hardcover proceedings, lunch, refreshments & dinner on December 27, 28 & 29 and lunch & refreshments on December 30. All Workshop activities will be held at the Oberoi, a 5 star hotel. Scholarships to full time students currently enrolled in universities in India are available. For details contact Professor Ravi Kumar at rkumar@ee.iitd.ernet.in. These scholarships are not available to students attending schools outside India. ... Tutorial Registration: ___________ Tutorial 1: HPF ... ___________ Tutorial 2: PVM Prog. ... ___________ Tutorial 3: Fortran M ... ___________ Tutorial 4: Scalability of ... ... Tutorial Fees: (Fee per tutorial) IEEE Member/Student Non-Member Advance Regsitration (Until Nov.25) Rs. 500 Rs. 600 Late/Onsite Registration (After Nov.26) Rs. 750 Rs. 900 Total Amount Enclosed: ___________________________ Payment must be enclosed. Please make cheques payable to International Workshop on Parallel Processing. All cheques MUST be either in U.S. Dollars drawn on a U.S. Bank or in Indian Rs. drawn on an Indian bank. Participants currently residing in India may pay in Indian Rs., all others (including NRIs) must pay in US Dollars. The exchange rate is set at US $1 = Indian Rs. 31.50. All fees must be converted using this rate. Please Mail to: IWPP '94 c/o Suresh Chalasani IWPP '94 c/o A. K. P. Nambiar ECE Dept, 1415 Johnson Dr. or to: C-DAC University of Wisconsin 2/1, Brunton Road Madison, WI 53706-1691, USA Bangalore, 560025, India Email: suresh@ece.wisc.edu Email: nambiar@cdacb.ernet.in Participants currently residing in India are requested to send their registration material to Mr. Nambiar, all others are requested to send them to Professor Chalasani. See next page for Registration Notes IWPP '94 HOTEL RESERVATION The Workshop will be held at the following address. The Oberoi 37-39, Mahatma Gandhi Road Bangalore 560 001, India Tel: 91-80-558 5858 Fax: 91-80-558 5960 A block of rooms has been reserved for the workshop participants. The special IWPP '94 rates are US $ 129.50 (per night, single or double). This rate includes all applicable taxes at the time of this publication. Please make room reservations directly with the hotel or through Datalead Worldwide Reservations System. Some toll free numbers are listed below. Please check with your travel consultant for additional Datalead reservations information. While making reservations use the group name "International Workshop on Parallel Processing." The cut off date for reservations is December 10. Since December is a busy time for travel in India, you may want to reserve your room in advance. Datalead Reservations Worldwide Telephone Numbers USA & CANADA: 1-800-5-OBEROI toll free, New York City 752-6565 local. EUROPE: United Kingdom 0800 515 517 toll free, Germany 0130 82 42 22 toll free, Belgium 078,11 04 71 toll free, Denmark 80 01 85 93 toll free, France 05 90 86 07 toll free, Netherlands 06 022 9702 toll free, Norway 050 11017 toll free, Spain 900 200104 toll free, Sweden 020 792922 toll free, Switzerland 155 2737 toll free, Italy 1678-25107 toll free. ASIA/PACIFIC: Australia 008 802 509 toll free, Sydney 233 4016 local, Hong Kong 800 2595 toll free, Japan 0120 025 725 toll free, Tokyo 5210 5135 local, Malaysia 800 1081 toll free, New Zealand 0800 44 1647 toll free, Singapore 737 0005 local. IWPP '94 REGISTRATION NOTES Written requests for workshop fee refunds must be received by your Finance Co-Chair by no later than November 25. Refunds are subject to a US $25 (Rs. 250 for tutorials) processing fee. All no-show registrations will be billed in full. Registrations after November 26 will be accepted on-site only. The registration desk will be open for on-site registration from 8 AM to 6 PM during December 26 - December 30 and from 8 AM to 12 Noon on December 31. Major credit cards will be accepted on-site for Workshop registration. -- Dhabaleswar K. Panda, Asst. Professor e-mail: panda@cis.ohio-state.edu Dept. of Computer and Information Science Office: (614) 292-5199 (Tel) Ohio State University, Columbus, OH 43210-1277, USA. (614) 292-2911 (Fax)