NOTE: Deadline for guaranteed hotel registration is March 22! Deadline for early conference registration is May 15. ADVANCE PROGRAM 22nd INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA) Santa Margherita Ligure, Italy June 18-24, 1995 Sponsored by the ACM and the IEEE Computer Society in cooperation with the University of Genoa, with the support of SGS-Thomson- Microelectronics and Olivetti. For more information, see the ISCA WWW page: http://www.cs.wisc.edu/~arch/www/isca95/ This Web page includes complete tutorial and workshop information, a copy of this advance program, conference and registration forms, travel information, maps, pictures and more. ============================================================================= Sunday, June 18th ----------------- TUTORIALS (see WWW page for more information) Full day: High Performance Microprocessors (FD1.1) Trevor Mudge, David Nagle, Richard Uhlig, Michael Upton, Univ. of Michigan, Carnegie Mellon University, German National Research Center for Computer Science, Intel Corporation Introduction to Parallel Computing (FD1.2) Mary Eshaghian, New Jersey Institute of Technology Morning: Introducing Parallel Databases for OLTP and Query Processing to Computer Architects (HD1.1) Honesty C. Young, IBM Almaden Afternoon: Reliable, Parallel Storage Architectures: RAID and Beyond (HD1.2) Garth Gibson, Carnegie Mellon University ============================================================================= Monday, June 19th and Tuesday, June 20th ---------------------------------------- WORKSHOPS 1. Undergraduate Computer Architecture Education Organizers: David Kaeli and Alessandro De Gloria Contact Person: David Kaeli, kaeli@nuvlsi.coe.neu.edu, (617)-373-5413, FAX (617)-373-8970 Date: Monday, June 19, 1995 Description: The focus of this workshop will be on Undergraduate Computer Architecture tools and methods currently being used throughout the world. The purpose is to provide a forum to disseminate information on these tools and methods, and to debate the current trends in undergraduate Computer Architecture curriculum. The attendees should come away from the workshop with improved tools and methods, that can implemented in their Computer Architecture curriculum. 2. Pre-hardware performance analysis techniques: how good are we at this? Organizer: Pradip Bose Contact Person: Pradip Bose, bose@watson.ibm.com OR bose@ausvm6.austin.ibm.com (914)-945-3478 OR (512)-838-6408 Date: Tuesday, June 20, 1995 Description: This workshop addresses the problem of pre-hardware processor/system performance analysis and design trade-offs. The effectiveness and accuracy of such models (or lack thereof) is ultimately borne out by post-hardware measurements, if and when the product is deployed. This day-long session features presentations from actual performance architects and application analysts, representing RISC super-scalar product vendors as well as academic research groups engaged in high performance processor/system design or development. The goal is to be able to examine the current state-of-the art in performance analysis and verification, as projected by the leading R&D groups in the area. The topics to be covered include: 1. static, source-driven vs dynamic, trace-driven models; -- the former includes analytical bounds models -- the latter includes classical "cycle timers" 2. representative trace generation and workload characterization; 3. performance model validation and formal verification; 4. pre-hardware design tuning techniques; -- including CPI vs CT trade-offs; compiler issues We will examine every facet of the net performance equation leading to published SPEC (and similar) numbers and debate how best to interpret these numbers in specific instances. Adequate time for in-depth discussion sessions following each paper-session is being budgeted for. 3. Multithreaded Architectures Organizers: Wim Bohm, Jean-Luc Gaudiot, and Walid Najjar Contact Person: Wim Bohm, bohm@cs.colostate.edu, (303)-491-7595 Dates: Monday and Tuesday, June 19 and 20, 1995 Description: This workshop will discuss the threaded model of execution, compilation issues, and multithreaded architectures. Threads can be either blocking or non-blocking. For blocking threads the processor must handle suspension and resumption of threads along with saving and restoring their states. Non-blocking threads implement a strict firing rule where all the inputs need to be present before the thread execution starts. Threads can be generated from functional languages with relative ease. These languages, however, do not have a very wide user base. Alternatively, traditional languages, can be extended with threads, or threads can be identified implicitly. In many respects, the multithreaded computation model can be seen as combining the advantages of both the von Neumann and dataflow models: efficient exploitation of instruction level locality of the former and the latency tolerance and efficient synchronization of the latter. 4. Fifth Workshop on Scalable Shared-Memory Multiprocessors Organizers: Michel Dubois and Ticky Thakker Contact Person: Michel Dubois, dubois@paris.usc.edu, (213)-740-4475, FAX (213)-740-7290 Dates: Monday and Tuesday, June 19 and 20, 1995 Description: This workshop covers all system aspects of scalable shared-memory multiprocessors. This includes, but is not limited to, the following topics: Multiprocessor Cache Coherence Cache-Only Memory Architectures Virtual Memory in Shared-Memory Systems Latency Tolerance and Hiding Shared-Memory on Networks of Workstations Virtual Shared Memory Systems Software Cache Coherence Benchmarking and Performance Evaluation High Performance IO Subsystem for Shared-memory Multiprocessors Fault Tolerance of Shared-memory Systems Update on Building Projects in Industry and in Academia You may submit multiple abstracts. Please note that the selection of your talk(s) for presentation is subject to relevance, current interest, and the availability of time slots. The work presented at the workshop can be work in progress or even proposals. Work in the process of being published elsewhere can also be presented. Presentations will be organized in sessions. At the end of each session, the speakers will form a panel to discuss with the audience the issues addressed in their talks. There will be no proceedings. ============================================================================= Wednesday, June 21st -------------------- TUTORIALS (see WWW page for more information) Full day: Parallelizing Compilers and Back-End Optimizations (FD2.1) Alex Nicolau, Constantine D. Polychronopoulos, Univ. of California at Irvine, Univ. of Illinois Distributed Shared Memory: Concepts and Systems (FD2.2) Jelica Protic, Milo Tomasevic, Veljko Milutinovic, Institute for Advanced Computer Technology Morning: A Methodology and Tool for Performance Prediction and Evaluation of Complex Computing Platforms (HD2.1) Giancarlo Cervetto, Alberto Nicelli, Antonio Schinco, Ludovico Messina, Olivetti Afternoon: Continuing to Exploit Instruction Level Parallelism: Issues, Bottlenecks, and Enabling Conditions (HD2.2) Yale N. Patt, Univ. of Michigan ---------------------------- Wednesday evening, June 21st --------------------------- Reception ============================================================================= Thursday, June 22nd ------------------- Welcome and Keynote Session 1: Multiprocessors and Applications 1) The MIT Alewife Machine: Architecture and Performance Anant Agarwal, Ricardo Bianchini (Univ. of Rochester), David Chaiken (DEC), Kirk L. Johnson, David Kranz, John Kubiatowicz, Beng-Hong Lim, Ken Mackenzie, Donald Yeung MIT, except as noted 2) The EM-X Parallel Computer: Architecture and Basic Performance Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai (Real World Computing Partnership), Yoshinori Yamaguchi Electrotechnical Laboratory (Japan), except as noted 3) Methodological Considerations and Characterization of the SPLASH-2 Parallel Application Suite Steven Cameron Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Shingh (Princeton University), Anoop Gupta Stanford University, except as noted Session 2A: Cache Coherence 1) Efficient Strategies for Software-Only Directory Protocols in Shared Memory Multiprocessors Hakan Grahn, Per Stenstrom Lund University (Sweden) 2) Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors Alvin R. Lebeck, David A. Wood University of Wisconsin 3) Boosting the Performance of Hybrid Snooping Cache Protocols Fredrik Dahlgren Lund University (Sweden) Session 2B: Interconnect Technology and I/O 1) S-Connect: from Networks of Workstations to Supercomputer Peformance Andreas G. Nowatzyk, Michael C. Bronwe, Edmund Kelly, Michael Parkin SUN Microsystems 2) Destage Algorithms for Disk Arrays with Nonvolatile Caches Anujan Varma, Quinn Jacobson University of California, Santa Cruz 3) Evaluating Multi-Port Frame Buffer Designs for a Mesh-Connected Multicomputer Gordon Stoll, Bin Wei, Douglas Clark, Edward W. Felten, Kai Li, Patrick Hanrahan (Stanford University) Princeton University, except where noted 4) Are Crossbars Really Dead? The Case for Optical Multiprocessor Interconnect Systems Andreas G. Nowatzyk (SUN Microsystems), Paul R. Prucnal (Princeton University) Session 3: Instruction Level Parallelism 1) Exploring Configurations of Functional Units in an Out-of-Order Superscalar Processor S. Jourdan, P. Sainrat IRIT (France) 2) Unconstrained Speculative Execution with Predicated State Buffering Hideki Ando, Chikako Nakanishi, Tetsuya Hara, Masao Nakaya Mitsubishi Electric Corp. (Japan) 3) A Comparison of Full and Partial Predicated Execution Support for ILP Processors Scott Mahlke, Richard Hank, James McCormick, David August, Wen-mei Hwu University of Illinois Evening Panel Session ============================================================================= Friday June 23 -------------- Session 4a: New Microarchitectures 1) Implementation Trade-offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor Mike Simone, Andrew Essen, Atsushi Ike, Anand Krishnamoorthy, Niteen Patkar, Murugappan Ramaswami, Viji Thirumalaiswamy HaL Computer Systems 2) Performance Evaluation of the PowerPC 620 Microarchitecture Christopher P. Nelson, Trung A. Diep, John P. Shen Carnegie Mellon University Session 4b: Managing Memory Hierarchies 1) Reducing TLB and Memory Overhead using Online Superpage Promotion Theodore H. Romer, Wayne H. Ohlrich, Anna R. Karlin, Brian N. Bershad University of Washington 2) Speeding up Irregular Applications in Shared-Memory Multiprocessors: Memory Binding and Group Prefetching Zheng Zhang, Josep Torrellas University of Illinois at Urbana-Champaign Session 5a: Interconnection Network Routing 1) An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA Anjan K. V., Timothy Pinkston University of Southern Calfornia 2) Analysis and Implementation of Hybrid Switching Kang G. Shin and Stuart W. Daniel University of Michigan 3) Configurable Flow Control Mechanisms for Fault-Tolerant Routing Binh Vien Dao, Jose Duato (Universidad Politecnica de Valencia, Spain), Sudhakar Yalamanchili Georgia Institute of Technology, except where noted 4) NIFDY: A Low Overhead, High Throughput Network Interface Timothy Callahan, Seth Copen Goldstein University of California, Berkeley Session 5B: Novel Memory Access Mechanisms 1) Vector Multiprocessors with Arbitrated Memory Access Montse Peiron, Mateo Valero, Eduard Aygaude', Tomas La'ng (University of California, Irvine) University of Catalonia (Spain), except where noted 2) Design of Cache Memories for Multi-Threaded Dataflow Architecture Krishna Kavi, Phenil Patadia, Elizabeth Abraham, Ponnarasu Shanmugam University of Texas at Arlington 3) Skewed Associativity Enhances Performance Predictability F. Bodin, Andre' Seznec IRISA/INRIA (France) ----------------------------------- Friday afternoon/evening, June 23rd ----------------------------------- Excursion and Banquet ============================================================================= Saturday June 24th ------------------ Session 6: Branch Prediction 1) A Comparative Analysis of Schemes for Correlated Branch Prediction Cliff Young, Nicholas Gloy, Michael D. Smith Harvard University 2) Next Cache Line and Set Prediction Brad Calder, Dirk Grunwald University of Colorado Session 7A: System Evaluation 1) A Comparison of Architectural Support for Messaging on the TMC CM-5 and Cray T3D Vijay Karamcheti, Andrew A. Chien University of Illinois 2) Optimizing Memory System Performance for Communications in Parallel Computers Thomas Stricker (Carnegie Mellon University), Thomas Gross (ETHZ and Carnegie Mellon University) 3) Empirical Evaluation of the CRAY-T3D: A Compiler Perspective Remzi H. Arpaci, David E. Culler, Arvind Krishnamurthy, Steve Steinberg, Katherine Yelick University of Calfornia, Berkeley Session 7B: Instruction Fetching 1) Optimization of Instruction Fetch Mechanisms for High Issue Rates Thomas M. Conte, Patrick M. Mills, Kishore N. Menezes, Burzin A. Patel University of South Carolina 2) Instruction Fetching: Coping with Code Bloat Richard Uhlig (German National Center for Computer Science), David Nagle (Carnegie Mellon University), Trevor Mudge (University of Michigan) Stuart Sechrest (University of Michigan), Joel Emer (Digital Equipment Corp.) 3) Instruction Cache Fetch Policies for Speculative Execution Dennis Lee and Jean-Loup Baer (University of Washington), Brad Calder and Dirk Grunwald (University of Colorado) Awards Luncheon Session 8: Caches 1) Streamlining Data Cache Access with Fast Address Calculation Todd Austin, Dionisios Pnevmatikatos, Guri Sohi University of Wisconsin 2) CAT -- Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches Hong Wang, Tong Sun, Qing Yang University of Rhode Island Session 9: Processor Architecture 1) Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean M. Tullsen, Susan Eggers, Henry M. Levy University of Washington 2) Architecture Validation for Processors Richard C. Ho, C. Han Yang, Mark A. Horowitz, David L. Dill Stanford University 3) Multiscalar Processors Guri Sohi, Scott Breach, T. N. Vijaykumar University of Wisconsin ============================================================================= CONFERENCE CHAIRS: General Alessandro De Gloria, University of Genoa Program James E. Smith, University of Wisconsin Vice-chair North Amer. Joseph Fisher, HP Labs Vice-chair Europe David May, SGS-Thomson-Microelectronics Vice-chair Asia Mitsuo Saito, Toshiba Corporation Tutorials Mark D. Hill, University of Wisconsin Workshops Guri Sohi, University of Wisconsin Finance & Registration Alan Berenbaum, AT&T Bell Labs Finance, Europe Rosa Gatti, University of Genoa Publicity & Publications Steve Scott, Cray Research STEERING COMMITTEE: Claudio Adriani Olivetti Gianni Degli Antoni Universita di Milano Dante Del Corso Politecnico di Torino. Bill Dally MIT Arrigo Frisiani Universita di Genova Wen-mei Hwu Univ. of Illinois Norm Jouppi DEC Roberto Negrini Politecnico di Milano Yale Patt Univ. of Michigan Gianguido Rizzotto SGS-Thomson-Microelectronics Alan Smith University of California at Berkeley PROGRAM COMMITTEE: David Culler Univ. of California at Berkeley Bill Dally MIT Ed Davidson Univ. of Michigan Susan Eggers Univ. of Washington Joel Emer DEC Garth Gibson Carnegie Mellon University John Gurd Univ. of Manchester John Hennessy Stanford University Peter Hsu Silicon Graphics Mark Hill Univ. of Wisconsin Wen-mei Hwu Univ. of Illinois Mary Jane Irwin Pennsylvania State University William Jalby IRISA Norm Jouppi DEC Manolis Katevenis Univ. of Crete Monica Lam Stanford University Jai Menon IBM Mariagiovanna Sami Politecnico Milano Steve Scott Cray Research J. P. Singh Princeton University Norihisa Suzuki IBM Japan Mateo Valero Polytechnic University of Catalonia M. Vanneschi Univ. of Pisa Pen Yew Univ. of Minnesota. REGISTRATION: Early registration must be postmarked by May 15, 1995. Full payment in U.S. dollars must accompany registration, either by check or a charge to MasterCard, Visa, or American Express. Registration by credit card may be faxed to the registration chair. Conference registration includes one copy of the proceedings, a ticket for a reception, the awards luncheon, an excursion into the Italian countryside which will include a banquet, and coffee breaks. Tutorial registration includes tutorial materials and coffee breaks. The student registration does not include banquets, and must be accompanied by a copy of a valid, full-time student ID. CONFERENCE SITE AND ACCOMMODATIONS: All technical sessions, tutorials, workshops, registration, lunch and the reception will be held at the Grand Hotel Miramare, Santa Margherita Ligure, near Portofino, Italy. Santa Margherita Ligure is located in the heart of the Italian Riviera. The Miramare is a luxury hotel, with a floral garden, an attended beach and a heated swimming pool. It is located directly on the bay. Grand Hotel Miramare lungomarae Milite Ignoto 30 16038 Santa Margherita Lig.(Ge), Italy Tel +39-185-287013 FAX +39-185-284651 Because the hotel will not be able to accommodate all attendees, it will be necessary to make hotel reservations through an agency in Italy. The agency, Portofino Coast Incoming, will book accommodations in a number of nearby hotels, in a wide variety of price ranges. A shuttle bus will be provided if it is necessary to book attendees at hotels more than a short walk from the Miramare. Call or fax Portofino Coast Incoming directly, using the form below, in the advance program brochure, or on the Web page. Because Santa Margherita is a popular resort area and late June is peak tourist season, Portofino Coast Incoming can only guarantee a hotel room adjacent to the conference site if reservations are made by March 22, 1995. They will continue to make reservations for conference attendees up to the end of the conference. WEATHER: The weather in the Italian Riviera in late June is predictably warm and sunny, with temperatures between 22C and 30C and scant chance of rain. GROUND TRANSPORTATION: Santa Margherita is located 30 kilometers from Genoa, the nearest major city, and about 5 km from Rapallo, a stop on the main rail line from Genoa to Rome. Portofino Coast Incoming can provide more detailed information on getting to Santa Margherita, if requested. They can also arrange for tours and excursions in the surrounding area. AIR TRANSPORTATION: Arrangements have been made with Thomas Cook Travel Management to provide air travel between the United States and Italy. The carrier is Delta Airlines. Thomas Cook guarantees that they will pro vide the lowest published airfares, but with the usual 7 day minimum stay requirement waived. They can also arrange ground or local air transportation in Europe, as well as pre or post conference tours. Please refer to ISCA when calling: Thomas Cook Convention and Incentive Services 100 Cambridge Park Drive Cambridge, MA 02140 Telephone: (800) 756-6125 TRAVEL SUPPORT FOR U.S. STUDENTS: We anticipate a group travel grant from the National Science Foundation and SIGARCH for student attendees of ISCA95. Individual awards will be in the amount of about $1,000 or the cost of round trip jet economy air fare whichever is less. Students presenting papers at the symposium will have priority. Other awards, if funds permit, will be given first to non-presenting student co-authors. Any member of the U.S. scientific community, irrespective of nationality, who performs work in the U.S. is eligible to apply. Special considerations will be given to minority applicants. Air travel must be on U.S. flag carriers. Applications will be accepted until April 1, 1995 and award recipients will be notified by May 1, 1995. For information and application forms, contact (preferably by e-mail): Jean-Loup Baer Department of Computer Science and Engineering, FR-35 University of Washington Seattle, Wa, 98195 baer@cs.washington.edu (206)-685-1376 WORLD WIDE WEB SITE: This year ISCA has a World Wide Web page, created by Doug Burger at the University of Wisconsin, with information about the conference. The address is: http://www.cs.wisc.edu/~arch/www/isca95/ On it can be found the advanced program, conference registration form, hotel reservation form, photographs of the conference site, maps of the area, description of workshops and tutorials, and more. WHILE YOU'RE AT IT: The International Conference on Parallel Architectures and Compilation Techniques, also sponsored by ACM SIGARCH and IEEE TCCA, is being held June 27-29 in Limassol, Cyprus. HOTEL REGISTRATION FORM The 22nd Annual International Symposium on COMPUTER ARCHITECTURE June 22-24, 1995 -- Santa Margherita Ligure, Italy Early hotel registration deadline: March 22, 1995 Please mark your choice of room from one of the following price classes by checking the appropriate box. All prices are PER PERSON in Italian Lira and include breakfast, service and taxes. In addition to the listed price, there will be an 8,000 Lira handling charge per person. At this writing approximately 1,600 Lira equal US$1. Hotel Class Single Room Double Room ----------------------------------------------------------- Four Star Deluxe [] 285,000 [] 258,000 Four Star Superior [] 135,000 - 160,000 [] 118,000 - 130,000 Four Star [] 111,000 - 132,000 [] 95,000 - 110,000 Three Star [] 85,000 - 105,000 [] 70,000 - 76,000 Two Star [] 75,000 - 85,000 [] 60,000 - 65,000 PLEASE PRINT OR TYPE: Name:__________________________________________________________________________ Organization:__________________________________________________________________ Address:_______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ Telephone:_____________________________________________________________________ E-Mail:________________________________________________________________________ Arrival date:_________________________ Departure date:________________________ To make the reservation, mail, telephone or fax: Portofino Coast Incoming Via Lamarmora, 17/6 16035 Rapallo (GE) Italy PHONE: +39-185-230185 FAX: +39-185-230054 The agency will respond with a letter or fax of confirmation, indicating the name of the hotel, the exact price as well as directions to the hotel. To hold the room, it will be necessary to pay a deposit, equivalent to one night's lodging for stays of three nights or less, or two night's lodging for stays of four nights or longer. The deposit can be paid by mailing a check to Portofino Coast Incoming (including an additional 5,000 Lira service charge for checks in Italian Lira or 10,000 Lira for checks in other currencies) or credit card. You may reuse this form to send the deposit. PLEASE INDICATE METHOD OF PAYMENT: [] Check payable to ISCA '95, in U.S. dollars [] MasterCard [] Visa [] American Express Total Enclosed:________________________________________________________________ Card Number:___________________________________________________________________ Expiration Date:_______________________________________________________________ Name on card:__________________________________________________________________ Signature:_____________________________________________________________________ REGISTRATION FORM The 22nd Annual International Symposium on COMPUTER ARCHITECTURE June 22-24, 1995 -- Santa Margherita Ligure, Italy Preregistration deadline May 15, 1995 Please mark your selection in the appropriate boxes: ACM/IEEE Member Non-Member Student* Early Late Early Late Early Late -------------------------------------------- $370 $450 $465 $560 $100 $125 Symposium [] [] [] [] [] [] -------------------------------------------- Full-Day Tutorial $250 $300 $310 $375 $100 $125 FD1.1 [] [] [] [] [] [] FD1.2 [] [] [] [] [] [] FD2.1 [] [] [] [] [] [] FD2.2 [] [] [] [] [] [] -------------------------------------------- Half-Day Tutorial $175 $210 $220 $260 $45 $70 HD1.1 [] [] [] [] [] [] HD1.2 [] [] [] [] [] [] HD2.1 [] [] [] [] [] [] HD2.2 [] [] [] [] [] [] *Note: student registration must be accompanied by a copy of a valid, full-time student id. PLEASE PRINT OR TYPE: Name:__________________________________________________________________________ Organization:__________________________________________________________________ Address:_______________________________________________________________________ _______________________________________________________________________ _______________________________________________________________________ Telephone:_____________________________________________________________________ E-Mail:________________________________________________________________________ [] ACM [] IEEE Member number:__________________________________________________ PLEASE INDICATE METHOD OF PAYMENT: [] Check payable to ISCA '95, in U.S. dollars [] MasterCard [] Visa [] American Express Total Enclosed:________________________________________________________________ Card Number:___________________________________________________________________ Expiration Date:_______________________________________________________________ Name on card:__________________________________________________________________ Signature:_____________________________________________________________________ Please complete and send this form to: ISCA '95 c/o Alan Berenbaum AT&T Bell Labs, Room 2C-325 600 Mountain Avenue Murray Hill, NJ 07974 USA fax +1-908-582-4417