Just When You thought It Was Safe To Go On Vacation HOT CHIPS SYMPOSIUM VI A Symposium on High-Performance Chips (Advance Program) Sponsored by the IEEE Computer Society Technical Committee on Microprocessors Stanford University, Palo, Alto, California Memorial Auditorium August 14-16, 1994 Attend HOT Chips VI, a symposium on high-performance chips, which will bring together researchers and developers of chips used to construct high-performance workstations and systems. Enjoy the informal format offering interaction with speakers. The first five HOT Chips Symposiums were huge successes and prompted articles in five special issues of IEEE Micro magazine. This year's HOT Chips VI will again bring you the latest developments in chip technology. ORGANIZING COMMITTEE General Chairman: John Mashey, Silicon Graphics Vice Chairman: Nam Ling, Santa Clara University Program Co-Chairmen: Alan J. Smith, UC Berkeley Don Alpert, Intel Finance Chairman: Dennis Reinhardt, Intel Registration Chairman: Robert Stewart, Stewart Research Publication Chairman: David Gustavson, SCI Technical Consortium Publicity Chairman: S. Diane Smith, Consultant Local Arrangements Chairmen: Alan Johnson, Cary Kornfeld, Interval Research Tutorials Chairman: Qiang Li Santa Clara University At Large: Martin Freeman, Philips Research John Hennessy, Stanford University PROGRAM COMMITTEE Donald Alpert, Intel (Program Co-Chairman) Forest Baskett, Silicon Graphics Alan Baum, Apple Computer Anoop Gupta, Stanford University Norman Jouppi DEC WRL Ruby Lee, Hewlett Packard Alan J. Smith, UC Berkeley (Program Co-Chairman) PROGRAM August 14, 1994 Tutorial Schedule: 7:30-8:30 Registration & Coffee at Memorial Auditorium 8:30-12:00 Algorithms & Hardware for Video Compression 12:00-1:00 Lunch 1:00-4:30 Instruction-Set Extension for Multiprocessor Interconnects 4:30-6:00 Wine & Cheese Reception in the Dohrman Grove Just North of the Hoover Tower on Serra Street Tutorial 1: Algorithms & Hardware for Video Compression Teresa Meng, Stanford University This tutorial will give an overview of the industry standards for video compression, including compression algorithms, performance comparisons and hardware implementations. Fast algorithms to achieve real-time encoding and decoding will be one focus of this tutorial. Besides industry standards, recent developments in compression techniuqes, such as subband and wavelet filtering and vector quantization will be covered. Finally research activities in the area of low-power implementations for portable video applications will be surveyed. Tutorial 2: Instruction-Set Extensions for Multiprocessor Interconnects David James, Apple Computer Most instruction sets have been optimized for uniprocessor environments. To effectively utilize multiprocessors on scalable interconnects, processors need to support additional capabilities, including 64-bit addressing, a well-defined set of memory access capabilities (loads, stores, and locks), non-blocking interrupts and synchronized time-of-day clocks. As background, the constraints of a typical high-speed interconnect, ANSI/IEEE Std 1596-1992 Scalable Coherent Interface (SCI), are considered. We show that specialized signals (such as bus-lock and interrupt) as well as eavesdrop or broadcast-based protocols can be avoided, explicit lock instructions (such as fetch&add) scale better than LoadReserved- and StoreConditional-based instruction sequences, and mixed endian data types (big and little) require minimal hardware (but significant compiler) support. We show how these conditions impact the design of processor instruction-set extensions. August 15, 1994 9:00-9:15 Welcome and Opening Remarks John Mashey, General Chair Don Alpert, Alan Jay Smith, Program Co-Chairs 9:15-10:45 CPUs - 1 Session Chair: Norman Jouppi, DEC WRL . An Overview of the 21164 Alpha AXP Microprocessor Paul Rubinfeld, Digital Equipment Corp. . The Power2+ Processor David Shippy, IBM . A 500MHz 32b 0.4um CMOS RISC Processor (Gallop) Masakazu Yamashina, NEC Corporation 10:45-11:15 Break 11:15-12:45 Multiprocessor and Encryption Session Chair: Howard Sachs, Sun Microsystems . The Alewife CMMU: Addressing the Multiprocessor Communications Gap John Kubiatowicz, MIT . nCube3 Integrated MPP Node Processor Robert Duzett, nCube . A 100Kbit/sec Single Chip Modular Exponentiation Processor Holger Orup, Aarhus University, Denmark 12:45-2:15 Lunch 2:15-4:15 Networks, Communications Session Chair: Forest Baskett, Silicon Graphics . UAI2110: An Universal GaAs ATM Interface Chip for High Speed Networks Premysl Vaclavik, Thomas Neuroth GmbH, Austria . CDMA Cellular Single Chip Cell Site Modem Ken Easton, Qualcomm, Inc. . A 500 MHz BiCMOS GByte/Second SCI-Link Implementation Wayne Nation, IBM . The STC104 Asynchronous Packet Switch Peter Thompson, INMOS Ltd. 4:15-4:45 Break 4:45-6:15 CPUs - 2 Session Chair: Don Alpert, Intel . The New i960 CPU that offers More for Less, the P100 Richard Brunner/Deif Atallah, Intel . SH-II- A Low Power RISC Micro for Consumer Applications Shumpei Kawasaki, Hitachi . Breaking the Traditional RISC Rules (A new family of scalable microprocessor cores) Gideon Intranter, National Semiconductor 6:15-7:45 Buffet Dinner 7:45-9:45 Evening Panel Session The Investor (Venture) Community View of What's Hot Moderator: Forest Baskett August 16, 1994: 8:30-10:00 Chipsets Session Chair: Allen Baum, Apple Computer . A PCI Bus ChipSet with Graphics Acceleration Jesse Lawrendra, Vertex Semiconductor Corp. . 82430NX PCIset: Companion to the Highest Performance Pentium Processor Patrick Correia, Intel Corporation . A Power PC/PCI Bridge Chip with a Cache and Memory Controller Karl Wang, Motorola, Inc. 10:00-10:30 Break 10:30-12:30 Graphics Session Chair: Ruby Lee, Hewlett Packard . An ASIC for Interactive 3D Graphics Stephanie Winner, Apple Computer Inc. . GLiNT - a 3D Graphiucs Processor Based on the OpenGL Standard Neil Trevett, DuPont Pixel . The Smart Frame Buffer Goes Hollywood: 3D and TV Joel McCormack, Digital Equipment Corporation . A Cached VRAM for 3D Graphics Michael Deering, SUN Microsystems 12:30-2:00 Lunch 2:00-3:30 Video Session Chair: Anoop Gupta, Stanford University . Video Compression Processor for H.320-to-Indeo Transcoding Brian Martin, Integrated Information Technology . A High Performance Programmable Multi-Standard Video Compression Chip Set David Still, Array Microsystems Inc. . Multimedia Enhancements for PA-RISC Processors Ruby Lee, Hewlett-Packard 3:30-4:00 Break 4:00-6:00 CPUs - 3 Session Chair: Alan J. Smith, UC Berkeley . PowerPC 604 S. Peter Song, IBM . The Thunder SPARC Processor Bruce Lightner, Metaflow Technologies Inc. . The Superscalar Hardware Architecture of the MC68060 Joe Circello, Motorola . A High Performance, Low Power, Pentium Processor Doug Carmean, Lawrence Clark, Robert Rozploch, Intel 6:00 Closing Remarks HOUSING INFORMATION Housing is available on the Stanford University campus in student dormatories which are vacant in the summer. These have central lavatory facilities and cost about $40 per night --- single, $50 per night --- double, for the nights of the symposium. A key deposit of $50 is required that will be refunded at checkout. Housing arrangements on the Stanford campus must be made by August 4 through HOT Chips, not Stanford. Housing is also available at numerous hotels and motels on the peninsula in Palo Alto, Menlo Park, Mountain View, and Los Altos within 5 miles of the campus. You are responsible for making such reservations directly with the motel. If you would like additional housing information, please check the housing information request box on the registration form. IEEE/Computer Society Membership To join call John Gill at (202) 371-0101. With confirmation, you may register for HOT Chips VI at member rates. QUESTIONS? For more information on registration and local arrangements contact Dr. Robert Stewart at (415) 941-6699 or r.stewart@compmail.com. REGISTRATION INCLUDES: * Attendance * Sunday Evening Wine & * One Copy of the Notes Cheese Reception * Two Luncheons * Monday Evening Reception * Coffee Breaks * Parking A Stanford map, parking permit, the location of parking, and a receipt will be mailed to early registrants. ON-SITE REGISTRATION is available Sunday morning before the tutorial and each morning at the Symposium. Early advanced registration is recommended because of the large attendance. Group discounts are available. CANCELLATION OF REGISTRATION: Must be made in writing prior to Sunday, August 7, 1994. A $40 fee will be charged for cancellation. FEDERAL TAX ID NUMBER IS: 13-1656633 for the Institute of Electrical & Electronic Engineers 345 E. 47th Street New York, NY 10017 Use certified mail for registration confirmation. ============================================================================= HOT CHIPS VI REGISTRATION FORM Name________________________________________________________________________ Organization________________________________________________________________ Dept/Mail Stop______________________________________________________________ Mailing Address_____________________________________________________________ City/State/Zip______________________________________________________________ Country_____________________________________________________________________ Area Code/Phone #___________________________________________________________ Email Address_______________________________________________________________ FAX_________________________________________________________________________ Membership: IEEE/CS______ ACM_______ Student______ None______ Society Membership Number___________________________________________________ Check One: ______Check drawn on a U.S. Bank ______MasterCard Make Check Payable To: Hot Chips Symposium ______VISA Name on Credit Card_________________________________________________________ Credit Card #_______________________________________________________________ Expiration Date_____________________________________________________________ Signature___________________________________________________________________ FEES: CIRCLE APPROPRIATE VALUES Before After July 22 July 22 IEEE/Computer Society $160 $230 or ACM Member Non-Member $230 $290 Student Member $55 $100 Sunday Tutorials, Member $30 $45 Tutorials, Non-Member $45 $60 Tutorials, Student $20 $30 Extra Copy of Notebook $30 $30 (with no mailing) Stanford University Dormitory Housing ______ nights @$40 per night single; $50 double $_________ Arrival__________________ Departure___________________ TOTAL AMOUNT PAID ______________ Electronic Registration, paid via VISA or Mastercard Registration: FAX: (415) 941-5048 EMAIL: r.stewart@compmail.com Surface Mail Registration To: Dr. Robert G. Stewart Stewart Research Enterprises 1658 Belvoir Drive Los Altos, CA 94024 Do NOT put me on the Hot Chips Mailing List _____ Stanford University Housing Information Requested _____