Discussion on Research in Network Processors
On November 14 and 16 we will have two discussion sessions on ongoing research in the area of network processors. Each team will lead a discussion based on a set of papers on a certain topic. We will discuss the first two topics (Architecture and Benchmarking) on November 14 and the last three (Programming Models, Network Applications and Novel Applications) on November 16. I have somewhat randomly assigned teams to topics. Note that you need a CMU IP address to access some of the papers.
Each team must prepare a set of slides that cover three issues. First, you briefly summarize and critique (positive and negative) the papers. Second, based on the papers, you try to describe the broader area that is covered by the papers. Three, you identify key topics for future work in the area. You should spend no more than a half of the time on the first topic, since everybody in class will have read at least one paper in each session. To help with the last two issues, I will meet with each team to talk about your presentation during the lab session of November 7.
Each session should be about 20 minutes, so plan on speaking for about 10 minutes. There is no need to prepare a big presentation – just a couple of slides that summarize key points is sufficient.
You are also required to read some additional papers for sessions that you are not organizing; in total everybody will read about 7 papers. I have attached the names (as symbols, 2a is the first member of the Team 2) of the readers to each paper in the list below. The goal is of course to make sure that everybody will be able to participate in the discussion. In order to prepare, please send me an e-mail message that summarizes key strengths and weaknesses of each paper for which you are a reader (bulleted lists are ok; no more than half a page).
Team 1: Broderick, Kao, Patel
Team 2: Singh, Paniker, Perneti
Team 3: Reddy, Kim Shawn
Team 4: O’Loughlin, Rivera
Team 5: Nychis, Sankaralingam, Sardesai
Architectures
(Team 1)
Overcoming the memory wall in packet processing: hammers or ladders? ,
Jayaram Mudigonda, Harrick M. Vin, Raj Yavatkar, Symposium On Architecture For
Networking And Communications System 2005,
Readers: 2a, 3a, 4a, 5a
Architectural impact of stateful networking applications , Javier
Verdú, Jorge Garcí, Mario Nemirovsky, Mateo Valero, Symposium On Architecture
For Networking And Communications System 2005,
Readers: 2b, 3b, 4b, 5b
A Case for Data Caching in Network Processors. Jayaram Mudigonda, Harrick M. Vin and Raj Yavatkar. Under Review.
Readers: 1c, 2c, 4b, 5c
Benchmarking
(Team 2)
Benchmarking
network processors, P.
Chandra, F. Hady, R. Yavatkar, T. Bock, M. Cabot, P. Mathew, in: P. Crowley, M.
Franklin, H. Hadimioglu, P. Onufryk (Eds.), Network Processor Design: Issues
and Practices, Vol. 1, Morgan Kaufmann Publishers, 2002, pp. 11--25.
Readers:
1b, 3a, 4a, 5b
Networking Processing Forum: IP Forwarding Application-level Benchmark, available from http://www.oiforum.com/public/Benchmarking_IAs.html.
Also: http://www.commsdesign.com/showArticle.jhtml?articleID=49400850
Readers: 1a, 3b, 5a
IXP2400
Intel Network Processor IPv6 Forwarding Benchmark Full Disclosure Report
for Gigabit Ethernet, June 16, 2003.
Available from the following web site: Performance
Benchmarks and Test Results
Readers: none
Programming
model (Team 5)
N. Shah,
http://www.gigascale.org/pubs/356/Shah-NP-Click.pdf
Readers: 1a, 2c, 3b, 4a
A Programming Environment for Packet-processing Systems: Design Considerations. Harrick M. Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze, and Ruiqi Lian, In the Workshop on Network Processors & Applications - NP3. Held in conjunction with The 10th International Symposium on High-Performance Computer Architecture February 14-18, 2004
Readers: 1b, 2a, 4b
Introduction to the Auto-Partitioning Programming Model, Intel in Communications
Readers: 1c, 2b, 3a, 5c
Automatic Multithreading and Multiprocessing of C programs for IXP, Long Li, Bo Huang, Jinquan Dai, Luddy Harrison, PPOPP’05.
Readers: 1c, 2b, 3a, 5c
Network
Applications (Team 4)
Impact of Network Protocols on Programmable Router Architectures, B. Hardekopf, T. Riche, J. Mudigonda, M. Dahlin, H.M. Vin, and J. Kaur, Submitted for publication, April 2003.
http://www.cs.utexas.edu/users/vin/pub/pdf/jspe03.pdf
Readers: 1c, 2b, 3a, 5a
Framework for supporting multi-service edge packet processing on network
processors , Arun Raghunath, Aaron Kunze, Erik J.
Johnson, Vinod Balakrishnan, Symposium On Architecture For Networking And
Communications System 2005,
Readers: 1a, 2c, 3b, 5b
SpliceNP: a TCP splicer using a network processor , Li Zhao, Yan Luo, Laxmi Bhuyan, Ravi Iyer, Symposium On Architecture For Networking And Communications System 2005, Princeton, October 26 - 28, 2005
Readers: 1b, 2a, 5c
Novel
Application (Team 3)
Exploiting Coarse-Grain
Parallelism to Accelerate Protein Motif Finding with a Network Processor,
B. Wun, J. Buhler, and P. Crowley, Proceedings
of the 2005 International Conference on Parallel Architectures and Compilation
Techniques (PACT).
Readers: 1c, 2a, 4a, 5b
Addressing data compatibility on programmable network platforms ,
Ada Gavrilovska, Karsten Schwan, Symposium On Architecture For Networking And
Communications System 2005,
Readers: 1a, 2b, 4b, 5c
On the feasibility
of using network processors for DNA processing , Bos and Huang, [PDF version]
(Proceedings of NP3, Workshop on Network Processors & Applications,
Readers: 1b, 2c, 5a