-- Yunshan's bug report Wed Aug 12 12:23:02 EDT 1998
-- total vars 89
VAR 
  ref_0_impl_content[3]
  ref_0_spec_content[3]
 pc[3]
 dst[2]
 src1[2]
 src2[2]
  rs_0_busy[1]
  rs_0_inst_idx[3]
  rs_0_v_i_flag[2]
  rs_0_v_j_flag[2]
  rs_0_v_i[3]
  rs_0_v_j[3]
  rs_1_busy[1]
  rs_1_inst_idx[3]
  rs_1_v_i_flag[2]
  rs_1_v_j_flag[2]
  rs_1_v_i[3]
  rs_1_v_j[3]
  rs_2_busy[1]
  rs_2_inst_idx[3]
  rs_2_v_i_flag[2]
  rs_2_v_j_flag[2]
  rs_2_v_i[3]
  rs_2_v_j[3]
  rs_3_busy[1]
  rs_3_inst_idx[3]
  rs_3_v_i_flag[2]
  rs_3_v_j_flag[2]
  rs_3_v_i[3]
  rs_3_v_j[3]
  rg_0_flag[2]
  rg_0_content[3]
  rg_1_flag[2]
  rg_1_content[3]
  ref_0[3]
  fu_0_busy[1]
  fu_0_rs_idx[3]
  fu_0_inst_idx[3]
  fu_0_src1[3]
  fu_0_src1_flag[2]
  fu_0_src2[3]
  fu_0_src2_flag[2]
  fu_1_busy[1]
  fu_1_rs_idx[3]
  fu_1_inst_idx[3]
  fu_1_src1[3]
  fu_1_src1_flag[2]
  fu_1_src2[3]
  fu_1_src2_flag[2]
  bus_master[2]
  opcode[2]
  v_i_flag[2]
  v_j_flag[2]
  v_i[3]
  v_j[3]
  available_rs_idx[3]
  bad[3]
  c_value[2]
  c_rs_idx[2]
  c_pointer[2]
  c_bad[2]
  cdb_rs_idx[3]
  cdb_inst_idx[3]
  cdb_src1[3]
  cdb_src1_flag[2]
  cdb_src2[3]
  cdb_src2_flag[2]
  counter[2]
  print_cdb_rs_idx[3]
  print_cdb_inst_idx[3]
  print_cdb_src1[3]
  print_cdb_src1_flag[2]
  print_cdb_src2[3]
  print_cdb_src2_flag[2]
  print_available_rs_idx[3]
  fu_0_wl_rs_idx[3]
  fu_0_wl_inst_idx[3]
  fu_0_wl_src1[3]
  fu_0_wl_src1_flag[2]
  fu_0_wl_src2[3]
  fu_0_wl_src2_flag[2]
  print_fu_0_wl_rs_idx[3]
  print_fu_0_wl_inst_idx[3]
  print_fu_0_wl_src1[3]
  print_fu_0_wl_src1_flag[2]
  print_fu_0_wl_src2[3]
  print_fu_0_wl_src2_flag[2]
  fu_1_wl_rs_idx[3]
  fu_1_wl_inst_idx[3]
  fu_1_wl_src1[3]
  fu_1_wl_src1_flag[2]
  fu_1_wl_src2[3]
  fu_1_wl_src2_flag[2]
  print_fu_1_wl_rs_idx[3]
  print_fu_1_wl_inst_idx[3]
  print_fu_1_wl_src1[3]
  print_fu_1_wl_src1_flag[2]
  print_fu_1_wl_src2[3]
  print_fu_1_wl_src2_flag[2]

DEFINE
  pc := 4;
  bad := 7;
  c_value := 0;
  c_rs_idx := 1; 
  c_pointer := 2;
  c_bad := 3; 
  available_rs_idx := 
    case
      opcode = 0:
  	case
	!rs_0_busy : 0;
	!rs_1_busy : 1;
        1 : bad;
        esac;
      opcode = 1:
  	case
	!rs_2_busy : 2;
	!rs_3_busy : 3;
        1 : bad;
        esac;
    1 : bad;
    esac;
  cdb_rs_idx := case 
    bus_master = 0 & fu_0_ready : fu_0_rs_idx;
    bus_master = 1 & fu_1_ready : fu_1_rs_idx;
    1: bad ;
    esac;
  cdb_inst_idx := case 
    bus_master = 0 & fu_0_ready : fu_0_inst_idx;
    bus_master = 1 & fu_1_ready : fu_1_inst_idx;
    1: bad; 
    esac;
  cdb_src1 := case 
    bus_master = 0 & fu_0_ready : fu_0_src1;
    bus_master = 1 & fu_1_ready : fu_1_src1;
    1: bad; 
    esac;
  cdb_src1_flag := case 
    bus_master = 0 & fu_0_ready : fu_0_src1_flag;
    bus_master = 1 & fu_1_ready : fu_1_src1_flag;
    1: c_bad; 
    esac;
  cdb_src2 := case 
    bus_master = 0 & fu_0_ready : fu_0_src2;
    bus_master = 1 & fu_1_ready : fu_1_src2;
    1: bad; 
    esac;
  cdb_src2_flag := case 
    bus_master = 0 & fu_0_ready :
	     fu_0_src2_flag;
    bus_master = 1 & fu_1_ready :
	     fu_1_src2_flag;
    1: c_bad; 
    esac;
  fu_0_wl_rs_idx := case 
    rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : 0;
    rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : 1;
    1: bad;
    esac;
  fu_0_wl_inst_idx := case 
    rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : rs_0_inst_idx;
    rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : rs_1_inst_idx;
    1: bad;
    esac;
  fu_0_wl_src1 := case 
  rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : rs_0_v_i;
  rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : rs_1_v_i;
  1: bad;
  esac;
  fu_0_wl_src1_flag := case 
    rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : rs_0_v_i_flag;
    rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : rs_1_v_i_flag;
    1: c_bad;
    esac;
  fu_0_wl_src2 := case 
    rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : rs_0_v_j;
    rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : rs_1_v_j;
    1: bad;
    esac;
  fu_0_wl_src2_flag := case 
    rs_0_busy & !(rs_0_v_i_flag = c_rs_idx) 
	& !(rs_0_v_j_flag = c_rs_idx) : rs_0_v_j_flag;
    rs_1_busy & !(rs_1_v_i_flag = c_rs_idx) 
	& !(rs_1_v_j_flag = c_rs_idx) : rs_1_v_j_flag;
    1: c_bad;
    esac;
  fu_1_wl_rs_idx := case 
    rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : 2;
    rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : 3;
    1: bad;
    esac;
  fu_1_wl_inst_idx := case 
    rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : rs_2_inst_idx;
    rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : rs_3_inst_idx;
    1: bad;
    esac;
  fu_1_wl_src1 := case 
  rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : rs_2_v_i;
  rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : rs_3_v_i;
  1: bad;
  esac;
  fu_1_wl_src1_flag := case 
    rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : rs_2_v_i_flag;
    rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : rs_3_v_i_flag;
    1: c_bad;
    esac;
  fu_1_wl_src2 := case 
    rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : rs_2_v_j;
    rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : rs_3_v_j;
    1: bad;
    esac;
  fu_1_wl_src2_flag := case 
    rs_2_busy & !(rs_2_v_i_flag = c_rs_idx) 
	& !(rs_2_v_j_flag = c_rs_idx) : rs_2_v_j_flag;
    rs_3_busy & !(rs_3_v_i_flag = c_rs_idx) 
	& !(rs_3_v_j_flag = c_rs_idx) : rs_3_v_j_flag;
    1: c_bad;
    esac;
  v_i_on_cdb := case 
    src1 = 0 & (rg_0_flag = c_rs_idx) & (rg_0_content =
	cdb_rs_idx) : 1; 
    src1 = 1 & (rg_1_flag = c_rs_idx) & (rg_1_content =
	cdb_rs_idx) : 1; 
    1: 0;
    esac; 
  v_j_on_cdb := case 
    src2 = 0 & (rg_0_flag = c_rs_idx) & (rg_0_content =
	cdb_rs_idx) : 1; 
    src2 = 1 & (rg_1_flag = c_rs_idx) & (rg_1_content =
	cdb_rs_idx) : 1; 
    1: 0;
    esac; 
  v_i_flag := case 
    v_i_on_cdb: c_pointer; 
    src1 = 0: rg_0_flag;
    src1 = 1: rg_1_flag;
    1: c_bad; 
    esac; 
  v_j_flag := case 
    v_j_on_cdb: c_pointer; 
    src2 = 0: rg_0_flag;
    src2 = 1: rg_1_flag;
    1: c_bad; 
    esac; 
  v_i := case 
    v_i_on_cdb: cdb_inst_idx; 
    src1 = 0: rg_0_content;
    src1 = 1: rg_1_content;
    1: bad; 
    esac; 
  v_j := case 
    v_j_on_cdb: cdb_inst_idx; 
    src2 = 0: rg_0_content;
    src2 = 1: rg_1_content;
    1: bad; 
    esac; 
ASSIGN
init(ref_0_impl_content) := case 
  rs_0_busy & rs_0_inst_idx = 0: 
  case 
     !(rs_0_v_i_flag = c_rs_idx) : rs_0_v_i;
     rs_0_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_0_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_0_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_0_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_1_busy & rs_1_inst_idx = 0: 
  case 
     !(rs_1_v_i_flag = c_rs_idx) : rs_1_v_i;
     rs_1_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_1_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_1_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_1_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_2_busy & rs_2_inst_idx = 0: 
  case 
     !(rs_2_v_i_flag = c_rs_idx) : rs_2_v_i;
     rs_2_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_2_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_2_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_2_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_3_busy & rs_3_inst_idx = 0: 
  case 
     !(rs_3_v_i_flag = c_rs_idx) : rs_3_v_i;
     rs_3_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_3_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_3_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_3_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  1 : ref_0;
  esac;
next(ref_0_impl_content) := case 
  rs_0_busy & rs_0_inst_idx = 0: 
  case 
     !(rs_0_v_i_flag = c_rs_idx) : rs_0_v_i;
     rs_0_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_0_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_0_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_0_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_1_busy & rs_1_inst_idx = 0: 
  case 
     !(rs_1_v_i_flag = c_rs_idx) : rs_1_v_i;
     rs_1_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_1_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_1_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_1_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_2_busy & rs_2_inst_idx = 0: 
  case 
     !(rs_2_v_i_flag = c_rs_idx) : rs_2_v_i;
     rs_2_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_2_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_2_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_2_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_3_busy & rs_3_inst_idx = 0: 
  case 
     !(rs_3_v_i_flag = c_rs_idx) : rs_3_v_i;
     rs_3_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_3_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_3_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_3_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  1 : ref_0;
  esac;
  init(ref_0) := bad;
init(counter) := 0; 
next(counter) := inc(counter); 
init(ref_0_spec_content) := case 
  rs_0_busy & rs_0_inst_idx = 0: 
  case 
     !(rs_0_v_i_flag = c_rs_idx) : rs_0_v_i;
     rs_0_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_0_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_0_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_0_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_1_busy & rs_1_inst_idx = 0: 
  case 
     !(rs_1_v_i_flag = c_rs_idx) : rs_1_v_i;
     rs_1_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_1_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_1_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_1_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_2_busy & rs_2_inst_idx = 0: 
  case 
     !(rs_2_v_i_flag = c_rs_idx) : rs_2_v_i;
     rs_2_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_2_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_2_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_2_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  rs_3_busy & rs_3_inst_idx = 0: 
  case 
     !(rs_3_v_i_flag = c_rs_idx) : rs_3_v_i;
     rs_3_v_i = 0 & rs_0_busy : rs_0_inst_idx;
     rs_3_v_i = 1 & rs_1_busy : rs_1_inst_idx;
     rs_3_v_i = 2 & rs_2_busy : rs_2_inst_idx;
     rs_3_v_i = 3 & rs_3_busy : rs_3_inst_idx;
     1 : ref_0;
     esac;
  1 : ref_0;
  esac;
next(ref_0_spec_content) := ref_0_spec_content;

  next(bus_master) :=
    case 
      bus_master = 1 :  0; 
      1: inc(bus_master); 
    esac; 
  next(rs_0_busy) := case 
    available_rs_idx = 0 : 1;
    rs_0_busy & cdb_rs_idx = 0 : 0;
    1: rs_0_busy; 
    esac;
  next(rs_0_inst_idx) := case
    available_rs_idx = 0 : pc;
    1: rs_0_inst_idx; 
    esac;
  next(rs_0_v_i_flag) := case 
    available_rs_idx = 0 : v_i_flag;
    rs_0_busy & rs_0_v_i_flag = c_rs_idx & 
      rs_0_v_i = cdb_rs_idx : c_pointer; 
    1: rs_0_v_i_flag;
    esac;
  next(rs_0_v_i) := case 
    available_rs_idx = 0 : v_i;
    rs_0_busy & rs_0_v_i_flag = c_rs_idx & 
      rs_0_v_i = cdb_rs_idx : cdb_inst_idx; 
    1: rs_0_v_i;
    esac;
  next(rs_0_v_j_flag) := case 
    available_rs_idx = 0 : v_j_flag;
    rs_0_busy & rs_0_v_j_flag = c_rs_idx & 
      rs_0_v_j = cdb_rs_idx : c_pointer; 
    1: rs_0_v_j_flag;
    esac;
  next(rs_0_v_j) := case 
    available_rs_idx = 0 : v_j;
    rs_0_busy & rs_0_v_j_flag = c_rs_idx & 
      rs_0_v_j = cdb_rs_idx : cdb_inst_idx; 
    1: rs_0_v_j;
    esac;
  next(rs_1_busy) := case 
    available_rs_idx = 1 : 1;
    rs_1_busy & cdb_rs_idx = 1 : 0;
    1: rs_1_busy; 
    esac;
  next(rs_1_inst_idx) := case
    available_rs_idx = 1 : pc;
    1: rs_1_inst_idx; 
    esac;
  next(rs_1_v_i_flag) := case 
    available_rs_idx = 1 : v_i_flag;
    rs_1_busy & rs_1_v_i_flag = c_rs_idx & 
      rs_1_v_i = cdb_rs_idx : c_pointer; 
    1: rs_1_v_i_flag;
    esac;
  next(rs_1_v_i) := case 
    available_rs_idx = 1 : v_i;
    rs_1_busy & rs_1_v_i_flag = c_rs_idx & 
      rs_1_v_i = cdb_rs_idx : cdb_inst_idx; 
    1: rs_1_v_i;
    esac;
  next(rs_1_v_j_flag) := case 
    available_rs_idx = 1 : v_j_flag;
    rs_1_busy & rs_1_v_j_flag = c_rs_idx & 
      rs_1_v_j = cdb_rs_idx : c_pointer; 
    1: rs_1_v_j_flag;
    esac;
  next(rs_1_v_j) := case 
    available_rs_idx = 1 : v_j;
    rs_1_busy & rs_1_v_j_flag = c_rs_idx & 
      rs_1_v_j = cdb_rs_idx : cdb_inst_idx; 
    1: rs_1_v_j;
    esac;
  next(rs_2_busy) := case 
    available_rs_idx = 2 : 1;
    rs_2_busy & cdb_rs_idx = 2 : 0;
    1: rs_2_busy; 
    esac;
  next(rs_2_inst_idx) := case
    available_rs_idx = 2 : pc;
    1: rs_2_inst_idx; 
    esac;
  next(rs_2_v_i_flag) := case 
    available_rs_idx = 2 : v_i_flag;
    rs_2_busy & rs_2_v_i_flag = c_rs_idx & 
      rs_2_v_i = cdb_rs_idx : c_pointer; 
    1: rs_2_v_i_flag;
    esac;
  next(rs_2_v_i) := case 
    available_rs_idx = 2 : v_i;
    rs_2_busy & rs_2_v_i_flag = c_rs_idx & 
      rs_2_v_i = cdb_rs_idx : cdb_inst_idx; 
    1: rs_2_v_i;
    esac;
  next(rs_2_v_j_flag) := case 
    available_rs_idx = 2 : v_j_flag;
    rs_2_busy & rs_2_v_j_flag = c_rs_idx & 
      rs_2_v_j = cdb_rs_idx : c_pointer; 
    1: rs_2_v_j_flag;
    esac;
  next(rs_2_v_j) := case 
    available_rs_idx = 2 : v_j;
    rs_2_busy & rs_2_v_j_flag = c_rs_idx & 
      rs_2_v_j = cdb_rs_idx : cdb_inst_idx; 
    1: rs_2_v_j;
    esac;
  next(rs_3_busy) := case 
    available_rs_idx = 3 : 1;
    rs_3_busy & cdb_rs_idx = 3 : 0;
    1: rs_3_busy; 
    esac;
  next(rs_3_inst_idx) := case
    available_rs_idx = 3 : pc;
    1: rs_3_inst_idx; 
    esac;
  next(rs_3_v_i_flag) := case 
    available_rs_idx = 3 : v_i_flag;
    rs_3_busy & rs_3_v_i_flag = c_rs_idx & 
      rs_3_v_i = cdb_rs_idx : c_pointer; 
    1: rs_3_v_i_flag;
    esac;
  next(rs_3_v_i) := case 
    available_rs_idx = 3 : v_i;
    rs_3_busy & rs_3_v_i_flag = c_rs_idx & 
      rs_3_v_i = cdb_rs_idx : cdb_inst_idx; 
    1: rs_3_v_i;
    esac;
  next(rs_3_v_j_flag) := case 
    available_rs_idx = 3 : v_j_flag;
    rs_3_busy & rs_3_v_j_flag = c_rs_idx & 
      rs_3_v_j = cdb_rs_idx : c_pointer; 
    1: rs_3_v_j_flag;
    esac;
  next(rs_3_v_j) := case 
    available_rs_idx = 3 : v_j;
    rs_3_busy & rs_3_v_j_flag = c_rs_idx & 
      rs_3_v_j = cdb_rs_idx : cdb_inst_idx; 
    1: rs_3_v_j;
    esac;

  next(rg_0_flag) := case 
    !(available_rs_idx = bad) & dst = 0: c_rs_idx;
    rg_0_flag = c_rs_idx & rg_0_content = cdb_rs_idx
      & !(cdb_rs_idx = bad) : c_pointer;
    1: rg_0_flag;
    esac;
  next(rg_0_content) := case
    !(available_rs_idx = bad) & dst = 0: available_rs_idx;
    rg_0_flag = c_rs_idx & rg_0_content = cdb_rs_idx
      & !(cdb_rs_idx = bad) : cdb_inst_idx;
    1: rg_0_content;
    esac;
  next(rg_1_flag) := case 
    !(available_rs_idx = bad) & dst = 1: c_rs_idx;
    rg_1_flag = c_rs_idx & rg_1_content = cdb_rs_idx
      & !(cdb_rs_idx = bad) : c_pointer;
    1: rg_1_flag;
    esac;
  next(rg_1_content) := case
    !(available_rs_idx = bad) & dst = 1: available_rs_idx;
    rg_1_flag = c_rs_idx & rg_1_content = cdb_rs_idx
      & !(cdb_rs_idx = bad) : cdb_inst_idx;
    1: rg_1_content;
    esac;

  next(fu_0_ready) := case 
    !fu_0_ready & fu_0_busy & !delay_0 : 1;
    fu_0_busy & (fu_0_rs_idx = cdb_rs_idx) & !(cdb_rs_idx = bad) : 0; 
    1: fu_0_ready;
    esac;
  next(fu_0_busy) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : 1;
    fu_0_busy & (fu_0_rs_idx = cdb_rs_idx) & !(cdb_rs_idx = bad) : 0; 
    1: fu_0_busy;
    esac;
  next(fu_0_rs_idx) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_rs_idx;
    1: fu_0_rs_idx;
   esac;
  next(fu_0_inst_idx) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_inst_idx;
    1: fu_0_inst_idx;
   esac;
  next(fu_0_src1) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_src1;
    1: fu_0_src1;
   esac;
  next(fu_0_src1_flag) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_src1_flag;
    1: fu_0_src1_flag;
   esac;
  next(fu_0_src2) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_src2;
    1: fu_0_src2;
   esac;
  next(fu_0_src2_flag) := case 
    !fu_0_busy & !(fu_0_wl_rs_idx = bad) : fu_0_wl_src2_flag;
    1: fu_0_src2_flag;
   esac;
  next(fu_1_ready) := case 
    !fu_1_ready & fu_1_busy & !delay_1 : 1;
    fu_1_busy & (fu_1_rs_idx = cdb_rs_idx) & !(cdb_rs_idx = bad) : 0; 
    1: fu_1_ready;
    esac;
  next(fu_1_busy) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : 1;
    fu_1_busy & (fu_1_rs_idx = cdb_rs_idx) & !(cdb_rs_idx = bad) : 0; 
    1: fu_1_busy;
    esac;
  next(fu_1_rs_idx) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_rs_idx;
    1: fu_1_rs_idx;
   esac;
  next(fu_1_inst_idx) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_inst_idx;
    1: fu_1_inst_idx;
   esac;
  next(fu_1_src1) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_src1;
    1: fu_1_src1;
   esac;
  next(fu_1_src1_flag) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_src1_flag;
    1: fu_1_src1_flag;
   esac;
  next(fu_1_src2) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_src2;
    1: fu_1_src2;
   esac;
  next(fu_1_src2_flag) := case 
    !fu_1_busy & !(fu_1_wl_rs_idx = bad) : fu_1_wl_src2_flag;
    1: fu_1_src2_flag;
   esac;
  next(ref_0) := case
    cdb_inst_idx = 0: cdb_src1;
    1:	ref_0;
    esac;
init(print_cdb_rs_idx) :=  cdb_rs_idx ;
init(print_cdb_inst_idx) := cdb_inst_idx ;
init(print_cdb_src1) := cdb_src1 ; 
init(print_available_rs_idx) := available_rs_idx;
  init(print_fu_0_wl_rs_idx) := fu_0_wl_rs_idx ; 
  init(print_fu_0_wl_inst_idx) := fu_0_wl_inst_idx ; 
  init(print_fu_0_wl_src1) := fu_0_wl_src1 ; 
  init(print_fu_0_wl_src1_flag) := fu_0_wl_src1_flag ; 
  init(print_fu_1_wl_rs_idx) := fu_1_wl_rs_idx ; 
  init(print_fu_1_wl_inst_idx) := fu_1_wl_inst_idx ; 
  init(print_fu_1_wl_src1) := fu_1_wl_src1 ; 
  init(print_fu_1_wl_src1_flag) := fu_1_wl_src1_flag ; 
next(print_cdb_rs_idx) :=  cdb_rs_idx ;
next(print_cdb_inst_idx) := cdb_inst_idx ;
next(print_cdb_src1) := cdb_src1 ; 
next(print_available_rs_idx) := available_rs_idx;
  next(print_fu_0_wl_rs_idx) := fu_0_wl_rs_idx ; 
  next(print_fu_0_wl_inst_idx) := fu_0_wl_inst_idx ; 
  next(print_fu_0_wl_src1) := fu_0_wl_src1 ; 
  next(print_fu_0_wl_src1_flag) := fu_0_wl_src1_flag ; 
  next(print_fu_1_wl_rs_idx) := fu_1_wl_rs_idx ; 
  next(print_fu_1_wl_inst_idx) := fu_1_wl_inst_idx ; 
  next(print_fu_1_wl_src1) := fu_1_wl_src1 ; 
  next(print_fu_1_wl_src1_flag) := fu_1_wl_src1_flag ; 
INIT


!(rs_0_inst_idx = rs_1_inst_idx) &
!(rs_0_inst_idx = rs_2_inst_idx) &
!(rs_0_inst_idx = rs_3_inst_idx) &
!(rs_1_inst_idx = rs_2_inst_idx) &
!(rs_1_inst_idx = rs_3_inst_idx) &
!(rs_2_inst_idx = rs_3_inst_idx) &

(fu_0_busy & fu_0_rs_idx = 0 -> fu_0_inst_idx = rs_0_inst_idx) &
(fu_0_busy & fu_0_rs_idx = 1 -> fu_0_inst_idx = rs_1_inst_idx) &
(fu_1_busy & fu_1_rs_idx = 2 -> fu_1_inst_idx = rs_2_inst_idx) &
(fu_1_busy & fu_1_rs_idx = 3 -> fu_1_inst_idx = rs_3_inst_idx) &
(fu_0_busy & fu_0_rs_idx = 0 -> fu_0_src1 = rs_0_v_i) &
(fu_0_busy & fu_0_rs_idx = 1 -> fu_0_src1 = rs_1_v_i) &
(fu_1_busy & fu_1_rs_idx = 2 -> fu_1_src1 = rs_2_v_i) &
(fu_1_busy & fu_1_rs_idx = 3 -> fu_1_src1 = rs_3_v_i) &
(fu_0_busy & fu_0_rs_idx = 0 -> fu_0_src1_flag = rs_0_v_i_flag) &
(fu_0_busy & fu_0_rs_idx = 1 -> fu_0_src1_flag = rs_1_v_i_flag) &
(fu_1_busy & fu_1_rs_idx = 2 -> fu_1_src1_flag = rs_2_v_i_flag) &
(fu_1_busy & fu_1_rs_idx = 3 -> fu_1_src1_flag = rs_3_v_i_flag) &
(fu_0_busy -> !(fu_0_src1_flag = 1)) &
(fu_1_busy -> !(fu_1_src1_flag = 1)) &

(ref_0_impl_content = 1 )&
	
	
(fu_0_busy & fu_0_rs_idx = 0 -> rs_0_busy) &
	
(fu_0_busy & fu_0_rs_idx = 1 -> rs_1_busy) &
	
(fu_1_busy & fu_1_rs_idx = 2 -> rs_2_busy) &
	
(fu_1_busy & fu_1_rs_idx = 3 -> rs_3_busy) &
	
(rg_0_flag = c_rs_idx & rg_0_content = 0 -> rs_0_busy) &
	  
(rg_0_flag = c_rs_idx & rg_0_content = 1 -> rs_1_busy) &
	  
(rg_0_flag = c_rs_idx & rg_0_content = 2 -> rs_2_busy) &
	  
(rg_0_flag = c_rs_idx & rg_0_content = 3 -> rs_3_busy) &
	  
(rg_1_flag = c_rs_idx & rg_1_content = 0 -> rs_0_busy) &
	  
(rg_1_flag = c_rs_idx & rg_1_content = 1 -> rs_1_busy) &
	  
(rg_1_flag = c_rs_idx & rg_1_content = 2 -> rs_2_busy) &
	  
(rg_1_flag = c_rs_idx & rg_1_content = 3 -> rs_3_busy) &
	  
!(available_rs_idx = bad) & 

( fu_0_rs_idx = 0 | fu_0_rs_idx = 1 | (a & ~a)) & 

 fu_0_ready =  fu_0_busy & !delay_0 &

( fu_1_rs_idx = 2 | fu_1_rs_idx = 3 | (a & ~a)) & 

 fu_1_ready =  fu_1_busy & !delay_1 &

( bus_master = 0 | bus_master = 1 | (a & ~a))  

--SPEC AG(counter = 2 -> ref_0_impl_content = ref_0_spec_content)
--SPEC AG((fu_1_busy & fu_1_rs_idx = 3 -> fu_1_src1_flag = 0))
SPEC AG
--(!(rs_0_inst_idx = rs_1_inst_idx) 
-- | (rs_0_inst_idx = 4)) &
--(fu_0_busy & fu_0_rs_idx = 0 -> fu_0_inst_idx = rs_0_inst_idx) &
(
--(fu_1_busy & fu_1_rs_idx = 2 -> fu_1_src1 = rs_2_v_i) &
--(fu_0_busy & fu_0_rs_idx = 0 -> fu_0_src1_flag = rs_0_v_i_flag) &
--(fu_0_busy -> !(fu_0_src1_flag = 1)) &
--(fu_0_busy & fu_0_rs_idx = 0 -> rs_0_busy) &
--(rg_0_flag = c_rs_idx & rg_0_content = 0 -> rs_0_busy) &
--( fu_0_rs_idx = 0 | fu_0_rs_idx = 1 | (a & ~a)) &
--( bus_master = 0 | bus_master = 1 | (a & ~a)) &
(ref_0_impl_content = 1 )&

(a # ~a)
)

